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參數(shù)資料
| 型號： | BRS2B16P |
| 英文描述： | Quad Differential Receivers BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A |
| 中文描述： | 四路差分接收器BRF1A，BRF2A，BRS2B，BRR1A和BRT1A |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 236K |
| 代理商： | BRS2B16P |
4
Agere Systems Inc.
Data Sheet
April 2001
BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A
Quad Differential Receivers
Timing Characteristics
Table 4. Timing Characteristics
(See Figure 4 and Figure 5.)
For propagation delays (t
PLH
and t
PHL
) over the temperature range, see Figure 9 and Figure 10.
Propagation delay test circuit connected to output is shown in Figure 6.
T
A
= –40 °C to +125 °C, V
CC
= 5 V
±
0.5 V.
12-3462(F)
Note: This graph is included as an aid to the system designers. Total circuit delay varies with load capacitance. The total delay is the sum of the
delay due to the external capacitance and the intrinsic delay of the device.
Figure 3. Typical Extrinsic Propagation Delay vs. Load Capacitance at 25 °C
Parameter
Symbol
Min
Typ
Max
Unit
Propagation Delay:
Input to Output High
Input to Output Low
Disable Time, C
L
= 5 pF:
High-to-high Impedance
Low-to-high Impedance
Pulse Width Distortion, ltpHL
tpLHI:
Load Capacitance (C
L
) = 15 pF
Load Capacitance (C
L
) = 150 pF
Output Waveform Skews:
Part-to-Part Skew, T
A
= 75 °C
Part-to-Part Skew, T
A
= –40 °C to +125 °C
Same Part Skew
Enable Time:
High Impedance to High
High Impedance to Low
Rise Time (20%—80%)
Fall Time (80%—20%)
t
PLH
t
PHL
1.5
1.5
2.5
2.5
4.0
4.0
ns
ns
t
PHZ
t
PLZ
—
—
5
5
12
12
ns
ns
tskew1
tskew1
—
—
—
—
0.7
4.0
ns
ns
tskew1p-p
tskew1p-p
tskew
—
—
—
0.8
—
—
1.4
1.5
0.3
ns
ns
ns
t
PZH
t
PZL
t
tLH
t
tHL
—
—
—
—
8
8
—
—
12
12
3.0
3.0
ns
ns
ns
ns
25
50
75
100
125
150
0
LOAD CAPACITANCE, C
L
(pF)
2
1
3
7
175
200
0
4
5
6
E
P
t
PHL
(TYP)
t
PLH
(TYP)
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