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參數(shù)資料
| 型號(hào)： | BRF2A16E |
| 英文描述： | Quad Differential Receivers BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A |
| 中文描述： | 四路差分接收器BRF1A，BRF2A，BRS2B，BRR1A和BRT1A |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 236K |
| 代理商： | BRF2A16E |
Agere Systems Inc.
7
Data Sheet
April 2001
BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A
Quad Differential Receivers
ESD Failure Models
Agere employs two models for ESD events that can
cause device damage or failure:
1. An HBM that is used by most of the industry for
ESD-susceptibility testing and protection-design
evaluation. ESD voltage thresholds are dependent
on the critical parameters used to define the model.
A standard HBM (resistance = 1500
,
capacitance = 100 pF) is widely used and, therefore,
can be used for comparison purposes.
2. A charged-device model (CDM), which many
believe is the better simulator of electronics
manufacturing exposure.
Table 5 and Table 6 illustrates the role these two
models play in the overall prevention of ESD damage.
HBM ESD testing is intended to simulate an ESD event
from a charged person. The CDM ESD testing
simulates charging and discharging events that occur in
production equipment and processes, e.g., an
integrated circuit sliding down a shipping tube.
The HBM ESD threshold voltage presented here was
obtained by using the following circuit parameters:
Table 5. Typical ESD Thresholds for Data
Transmission Receivers
Table 6. ESD Damage Protection
Device
HBM Threshold
CDM
Threshold
Differential
Inputs
>
800
Others
BRF1A, BRR1A,
BRT1A
BRF2A, BRS2B
>
2000
>
1000
>
2000
>
2000
>
2000
ESD Threat Controls
Personnel
Wrist straps.
ESD shoes.
Antistatic flooring.
Human body
model (HBM).
Processes
Static-dissipative
materials.
Air ionization.
Charged-device
model (CDM).
Control
Model
Latch Up
Latch-up evaluation has been performed on the data transmission receivers. Latch-up testing determines if power-
supply current exceeds the specified maximum due to the application of a stress to the device under test. A device
is considered susceptible to latch up if the power supply current exceeds the maximum level and remains at that
level after the stress is removed.
Agere performs latch up testing per an internal test method that is consistent with JEDEC Standard No. 17
(previously JC-40.2) CMOS Latch Up Standardized Test Procedure
Latch up evaluation involves three separate stresses to evaluate latch up susceptibility levels:
1. dc current stressing of input and output pins.
2. Power supply slew rate.
3. Power supply overvoltage.
Table 7. Latch Up Test Criteria and Test Results
Based on the results in Table 7, the data transmission receivers pass the Agere latch-up esting requirements and
are considered not susceptible to latch up.
dc Current Stress
of I/O Pins
≥
150 mA
Power Supply
Slew Rate
≤
1
μs
Power Supply
Overvoltage
≥
1.75 x Vmax
Data Transmission
Receiver ICs
Minimum Criteria
Test Results
≥
250 mA
≤
100 ns
≥
2.25 x Vmax
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