Am29F016 Flash memory. When linking the program, each 256 KBytes segment in the Am29F016 Flash is linked
separately. This allows for the linker to resolve subroutine accesses made from each separate segment of the
Am29F016 Flash with the commonly shared code in the Am29F010 Flash.
The key to using both the expanded data and expanded code address space is to partition the data or code from the top
down. At the highest level, the programmer must think about the code or data and its interaction with other parts of the
program. This is why subroutines that are executed only once (for example, code used for start up initialization) and
interrupt service routines are prime candidates for dividing into the additional segments. The nature of such code lends
itself to the high level division.
If the user wants to have a single bank of Flash or single bank of SRAM, the same idea can be used for breaking the 1
MByte address boundary. However, some additional care must now be taken with the interrupt service routines. Figure
2 shows the implementation of extended SRAM and Flash. LCS is the chip select to 1 MByte of SRAM. Two PIO to the
upper address of the SRAM splits the SRAM into four segments of 256K each. UCS is the chip select to 4 MBytes of
Am29F016 Flash. Four PIOs separate it into 8 segments of 512 KBytes each. The remaining 256 KBytes of address
space is available for peripherals specific to the embedded application.
On boot up, the integrated pull-ups of the Am186ES microcontroller PIOs let us access the 512 KBytes segment of the
Am29F016 containing the start up code. If the Am186ES microcontroller did not have the integrated pull-ups, then
external pull-ups would be required. Otherwise, the upper four address bits of the flash would float and you could not
reliably know which of the 8 segments of the Am29F016 was being accessed.
As in the examples of figure 1 and figure 2, the software switches the PIOs to change segments as required. What has
changed is that you can not know which SRAM or Flash segments the program will be in when an interrupt occurs. The
Am186ES microcontroller will always get the interrupt vector from the interrupt vector table starting at address 0. This
means the bottom 1 KByte of each segment of SRAM must have a copy of the interrupt vector table. By the same token,
you can not know which of the 8 512 KBytes segments of Flash the program will be in when the interrupt occurs. There
are two ways to handle this. One is to duplicate enough of the interrupt service routine in each 512 Kbytes segment of
Flash to change the PIOs to the correct 512 KBytes segment of Flash and 256 KBytes of SRAM. The other method is to
use the SRAM to contain the code needed to switch to the correct Flash and SRAM segments.
One side affect of this technique for breaking the 1 MByte boundary is the inherent protection of the expanded
segments. No segment can address another segment without first changing the PIOs. The stacks for interrupts and main
program can be maintained separately, lowering the chance that the maximum stack expansion for main program and
interrupt service routine could together overflow the allotted stack space.
Using these techniques greatly extends the range of 186 applications. The improved performance of the more up to date
implementations of the 186, like the Am186ES microcontroller, provides more than enough horsepower to implement the
additional code to switch the PIOs. All or part of these methods can be implemented to meet the specific needs of your
embedded application.
Am186, Am188, and E86 are trademarks of Advanced Micro Devices, Inc.
AMD is a registered trademark of Advanced Micro Devices, Inc.