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參數(shù)資料
| 型號： | BQ4845S |
| 英文描述： | Fast Recovery Glass Passivated Rectifier Diodes |
| 中文描述： | 實時時鐘 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 1155K |
| 代理商： | BQ4845S |
the data lines are driven to an indeterminate state until
t
AA
. If the address inputs are changed while CS and OE
remain low, output data remains valid for t
OH
(output
data hold time), but goes indeterminate until the next
address access.
Write Mode
The bq4845 is in write mode whenever WE and CS are
active.
The start of a write is referenced from the
latter-occurring falling edge of WE or CS. A write is ter-
minated by the earlier rising edge of WE or CS. The ad-
dresses must be held valid throughout the cycle. CS or
WE must return high for a minimum of t
WR2
from CS or
t
WR1
from WE prior to the initiation of another read or
writecycle.
Data-in must be valid t
DW
prior to the end of write and
remain valid for t
DH1
or t
DH2
afterward. OE should be
kept high during write cycles to avoid bus contention; al-
though, if the output bus has been activated by a low on
CS and OE, a low on WE disables the outputs t
WZ
after
WE falls.
Reading the Clock
Once every second, the user-accessible clock/calendar lo-
cations are updated simultaneously from the internal
real time counters. To prevent reading data in transi-
tion, updates to the bq4845 clock registers should be
halted. Updating is halted by setting the update trans-
fer inhibit (UTI) bit D3 of the control register E. As long
as the UTI bit is 1, updates to user-accessible clock loca-
tions are inhibited. Once the frozen clock information is
retrieved by reading the appropriate clock memory loca-
tions, the UTI bit should be reset to 0 in order to allow
updates to occur from the internal counters.
the internal counters are not halted by setting the UTI
bit, reading the clock locations has no effect on clock ac-
curacy. Once the UTI bit is reset to 0, the internal regis-
ters update within one second the user-accessible regis-
ters with the correct time. A halt command issued dur-
ing a clock update allows the update to occur before
freezing thedata.
Because
Setting the Clock
The UTI bit must also be used to set the bq4845 clock.
Once set, the locations can be written with the desired
information in BCD format. Resetting the UTI bit to 0
causes the written values to be transferred to the inter-
nal clock counters and allows updates to the user-
accessibleregisters toresumewithin onesecond.
Stopping and Starting the Clock Oscillator
The bq4845 clock can be programmed to turn off when
the part goes into battery back-up mode by setting
STOP to 0 prior to power down. If the board using the
bq4845 is to spend a significant period of time in stor-
age, the STOP bit can be used to preserve some battery
capacity. STOP set to 1 keeps the clock running when
V
CC
drops below V
SO
. With V
CC
greater than V
SO
, the
bq4845 clock runs regardless of thestateof STOP.
Power-Down/Power-Up Cycle
The bq4845 continuously monitors V
CC
for out-of-
tolerance. During a power failure, when V
CC
falls below
V
PFD
, the bq4845 write-protects the clock and storage
registers.
When V
CC
is below V
BC
(3V typical), the
power source is switched to BC.
storage data are sustained by a valid backup energy
source.
When V
CC
is above V
BC
, the power source is
V
CC
. Write-protection continues for t
CSR
time after V
CC
rises aboveV
PFD
.
RTC operation and
An external CMOS static RAM is battery-backed using
the V
OUT
and chip enable output pins from the bq4845.
As the voltage input V
CC
slews down during a power
failure, the chip enable output, CE
OUT,
is forced inactive
independent of thechip enableinput CE
IN.
5
Bits
Description
24/12
24- or 12-hour representation
ABE
Alarm interrupt enable in
battery-backup mode
AF
Alarm interrupt flag
AIE
Alarm interrupt enable
ALM0–ALM1
Alarm mask bits
BVF
Battery-valid flag
DSE
Daylight savings time enable
PF
Periodic interrupt flag
PIE
Periodic interrupt enable
PM/AM
PM or AM indication
PWRF
Power-fail interrupt flag
PWRIE
Power-fail interrupt enable
RS0–RS3
Periodic interrupt rate
STOP
Oscillator stop and start
UTI
Update transfer inhibit
WD0 - WD2
Watchdog time-out rate
Table 2. Clock and Control Register Bits
Aug. 1995
bq4845/bq4845Y
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BQ4845S- | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Parallel RTC With CPU Supervisor |
| BQ4845S-A4 | 功能描述:實時時鐘 w/NVSRAM Control Watchdog Timer RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| BQ4845S-A4G4 | 功能描述:實時時鐘 w/NVSRAM Control Watchdog Timer RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| BQ4845S-A4N | 功能描述:實時時鐘 w/NVSRAM Control Watchdog Timer RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| BQ4845S-A4NG4 | 功能描述:實時時鐘 w/NVSRAM Control Watchdog Timer RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
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