參數(shù)資料
型號: BQ4285LSNTR
廠商: TEXAS INSTRUMENTS INC
元件分類: XO, clock
英文描述: 1 TIMER(S), REAL TIME CLOCK, PDSO24
封裝: 0.300 INCH, PLASTIC, SOIC-24
文件頁數(shù): 12/30頁
文件大?。?/td> 1497K
代理商: BQ4285LSNTR
Block Diagram
standard CMOS SRAM nonvolatile during power-fail
conditions. During power-fail, the bq4285E/L auto-
matically write-protects the external SRAM and pro-
vides a VCC output sourced from the clock backup
battery.
Pin Descriptions
AD0–AD7
Multiplexed address/data input/
output
The bq4285E/L bus cycle consists of two
phases: the address phase and the data-
transfer phase. The address phase precedes
the data-transfer phase.
During the ad-
dress phase, an address placed on AD0–AD7
is latched into the bq4285E/L on the falling
edge of the AS signal.
During the data-
transfer phase of the bus cycle, the AD0–AD7
pins serve as a bidirectional data bus.
MOT
Bus type select input (PLCC package
only)
MOT selects bus timing for either Motorola
or Intel architecture.
This pin should be
tied to VCC for Motorola timing or to VSS for
Intel timing (see Table 1).
The setting should not be changed during
system operation. MOT is internally pulled
low by a 20K
resistor. For the DIP and
SOIC packages, this pin is internally con-
nected to VSS, enabling the bus timing for
the Intel architecture.
CS
Chip select input
CS should be driven low and held stable
during the data-transfer phase of a bus cy-
cle accessing the bq4285E/L.
2
Bus
Type
MOT
Level
DS
Equivalent
R/W
Equivalent
AS
Equivalent
Motorola
VCC
DS, E, or
Φ2
R/W
AS
Intel
VSS
RD,
MEMR, or
I/OR
WR,
MEMW, or
I/OW
ALE
Table 1. Bus Setup
Jan. 1999 B
bq4285E/L
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