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參數(shù)資料
| 型號： | BQ3287MT |
| 英文描述： | Avalanche Glass Passivated Bridge Rectifiers |
| 文件頁數(shù)： | 8/26頁 |
| 文件大?。?/td> | 831K |
| 代理商： | BQ3287MT |
Power-Down/Power-Up Cycle
The bq3285EC and bq3285LC power-up/power-down cy-
cles are different. The bq3285LC continuously monitors
V
CC
for out-of-tolerance. During a power failure, when
V
CC
falls below V
PFD
(2.53V typical), the bq3285LC write-
protects the clock and storage registers. The power source
is switched to BC when V
CC
is less than V
PFD
and BC is
greater than V
PFD
, or when V
CC
is less than V
BC
and V
BC
is less than V
PFD
. RTC operation and storage data are
sustained by a valid backup energy source. When V
CC
is
above V
PFD
, the power source is V
CC
. Write-protection con-
tinues for t
CSR
timeafter V
CC
rises aboveV
PFD
.
The bq3285E C continuously monitors V
CC
for out-of-
tolerance. During a power failure, when V
CC
falls below
V
PFD
(4.17V typical), the bq3285EC write-protects the
clock and storage registers. When V
CC
is below V
BC
(3V
typical), the power source is switched to BC. RTC opera-
tion and storage data are sustained by a valid backup
energy source.
When V
CC
is above V
BC
, the power
source is V
CC
. Write-protection continues for t
CSR
time
after V
CC
rises aboveV
PFD
.
Control/Status Registers
The four control/status registers of the bq3285E C/LC
are accessible regardless of the status of the update cy-
cle(seeTable4).
Register A
Register A programs:
n
Thefrequency of theperiodic event rate.
n
Oscillator operation.
n
Time-keeping
Register A provides:
n
Status of theupdatecycle.
RS0–RS3 - Frequency Select
These bits select the periodic interrupt rate, as shown in
Table3.
OS0–OS2 - Oscillator Control
These three bits control the state of the oscillator and
divider stages. A pattern of 010 or 011 enables RTC op-
eration by turning on the oscillator and enabling the fre-
quency divider. This pattern must be set to turn the os-
cillator on for the bq3285LC and to ensure that the
bq3285EC/LC will keep time in battery-backup mode. A
pattern of 11X turns the oscillator on, but keeps the fre-
quency divider disabled. When 010 is written, the RTC
begins its first updateafter 500ms.
UIP - Update Cycle Status
This read-only bit is set prior to the update cycle. When
UIP equals 1, an RTC update cycle may be in progress.
UIP is cleared at the end of each update cycle. This bit
is also cleared when the update transfer inhibit (UTI)
bit in register B is 1.
8
bq3285EC/LC
Register A Bits
4
OS0
7
6
5
3
2
1
0
UIP
OS2
OS1
RS3
RS2
RS1
RS0
7
-
6
-
5
-
4
-
3
2
1
0
RS3
RS2
RS1
RS0
7
-
6
5
4
3
-
2
-
1
-
0
-
OS2
OS1
OS0
7
6
-
5
-
4
-
3
-
2
-
1
-
0
-
UIP
July 1996
Reg.
Loc.
(Hex) Read Write
Bit Name and State on Reset
7 (MSB)
6
5
4
3
2
1
0 (LSB)
A
0A
Yes
Yes
1
UIP
na
OS2
na
OS1
na
OS0
na
RS3
na
RS2
na
RS1
na
RS0
na
B
0B
Yes
Yes
UTI
na
PIE
0
AIE
0
UIE
0
-
0
DF
na
HF
na
DSE
na
C
0C
Yes
No
INTF
0
PF
0
AF
0
UF
0
-
0
-
na
-
0
-
0
D
0D
Yes
No
VRT
na
-
0
-
0
-
0
-
0
-
0
-
0
-
0
Notes:
na = not affected.
1.
Except bit 7.
Table 4. Control/Status Registers
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