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參數(shù)資料
| 型號： | BQ3285LSS-N |
| 英文描述： | Avalanche Glass Passivated Bridge Rectifiers |
| 中文描述： | 實時時鐘 |
| 文件頁數(shù)： | 2/26頁 |
| 文件大小： | 831K |
| 代理商： | BQ3285LSS-N |
Block Diagram
Pin Descriptions
MOT
Bus type select input
MOT selects bus timing for either Motorola
or Intel architecture.
tied to V
CC
for Motorola timing or to V
SS
for
Intel timing (see Table 1).
should not be changed during system opera-
tion. MOT is internally pulled low by a 30K
resistor.
This pin should be
The setting
AD
0
–AD
7
Multiplexed address/data
input/output
The bq3285EC/LC bus cycle consists of two
phases: the address phase and the data-
transfer phase.
The address phase pre-
cedes the data-transfer phase. During the
address phase, an address placed on
AD
0
–AD
7
and EXTRAM is latched into the
bq3285EC/LC on the falling edge of the AS
signal.
During the data-transfer phase of
the bus cycle, the AD
0
–AD
7
pins serve as a
bidirectional data bus.
AS
Address strobe input
AS serves to demultiplex the address/data
bus. The falling edge of AS latches the ad-
dress on AD
0
–AD
7
and EXTRAM. This de-
multiplexing process is independent of the
CS signal.
For DIP and SOIC packages
with MOT = V
SS
, the AS input is provided a
signal similar to ALE in an Intel-based sys-
tem.
2
bq3285EC/LC
Bus
Type
MOT
Level
DS
Equivalent
R/W
Equivalent
AS
Equivalent
Motorola
V
CC
DS, E, or
Φ
2
R/W
AS
Intel
V
SS
RD,
MEMR, or
I/OR
WR,
MEMW, or
I/OW
ALE
Table 1. Bus Setup
BD328501.eps
P
Bus
I/F
μ
Power-
Fail
Control
Storage Registers
(114 Bytes)
User Buffer
(14 Bytes)
VOUT
Clock/Calendar, Alarm
and Control Bytes
Time-
Base
Oscillator
Control/Status
Registers
÷ 8
÷ 64
÷ 64
16 1 MUX
Interupt
Generator
Control/Calendar
Update
VCC
DS
AD0–AD7
CS
MOT
32K
INT
X1
X2
3
4
RST
R/W
AS
Storage Registers
(128 Bytes)
RCL
EXTRAM
Write
Protect
CS
BC
32K
Driver
July 1996
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