參數(shù)資料
型號(hào): BQ3285LCS
英文描述: Real-Time Clock
中文描述: 實(shí)時(shí)時(shí)鐘
文件頁(yè)數(shù): 6/26頁(yè)
文件大?。?/td> 831K
代理商: BQ3285LCS
32kHz Output
The bq3285EC/LC provides for a 32.768kHz output. For
the bq3285EC, the output is always active whenever V
CC
is valid (V
PFD
+ t
CSR
). The bq3285EC output is not af-
fected by the bit settings in Register A. Time-keeping
aspects, however, still require setting OS0-OS2.
bq3285LC output is active when the oscillator is turned
on by setting theOSC0-OSC2 bits in Register A.
The
Interrupts
The bq3285EC/LC allows three individually selected in-
terrupt events to generate an interrupt request. These
threeinterrupt events are:
n
The periodic interrupt, programmable to occur once
every 122
μ
s to500ms.
n
The alarm interrupt, programmable to occur once per
second to once per day, is active in battery-backup
mode, providing a “wake-up” feature.
n
The update-ended interrupt, which occurs at the end
of each updatecycle.
Each of the three interrupt events is enabled by an indi-
vidual interrupt-enable bit in register B. When an event
occurs, its event flag bit in register C is set. If the corre-
sponding event enable bit is also set, then an interrupt
request is generated.
The interrupt request flag bit
(INTF) of register C is set with every interrupt request.
Reading register C clears all flag bits, including INTF,
and makes INT high-impedance.
Two methods can be used to process bq3285EC/LC in-
terrupt events:
n
Enable interrupt
request output to invoke an interrupt service routine.
events and use the interrupt
n
Do not enable the interrupts and use a polling
routine to periodically check the status of the flag
bits.
The individual interrupt sources are described in detail
in thefollowing sections.
6
bq3285EC/LC
Register A Bits
RS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Periodic Interrupt
Period
None
3.90625
7.8125
122.070
244.141
488.281
976.5625
1.95315
3.90625
7.8125
15.625
31.25
62.5
125
250
500
same as above defined
by RS3–RS0
OSC2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OSC1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
OSC0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
RS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
RS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Units
ms
ms
μ
s
μ
s
μ
s
μ
s
ms
ms
ms
ms
ms
ms
ms
ms
ms
0
1
1
X
X
X
X
Table 3. Periodic Interrupt Rate
July 1996
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