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SLUS894 – JANUARY 2010
Pin Functions – 24-Pin QFN
PIN
FUNCTION DESCRIPTION
NO.
NAME
1
ACN
Adapter current sense resistor, negative input. A 0.1-mF ceramic capacitor is placed from ACN to ACP to provide differential-mode
filtering. An optional 0.1-mF ceramic capacitor is placed from ACN pin to GND for common-mode filtering.
2
ACP
Adapter current sense resistor, positive input. A 0.1-mF ceramic capacitor is placed from ACN to ACP to provide differential-mode
filtering. A 0.1-mF ceramic capacitor is placed from ACP pin to GND for common-mode filtering.
3
ACDRV
AC adapter to system MOSFET driver output. Connect through a 1-k
resistor to the gate of the ACFET P-channel power MOSFET
and the reverse conduction blocking P-channel power MOSFET. The internal gate drive is asymmetrical, allowing a quick turn-off and
slow turn-on, in addition to the internal break-before-make logic with respect to BATDRV. If needed, an optional capacitor from gate to
source of the ACFET is used to slow down the ON and OFF times.
4
CE
Charge-enable active-HIGH logic input. HI enables charge. LO disables charge. It has an internal 1M
pull-down resistor.
5
STAT1
Open-drain charge status pin to indicate various charger operation.
6
TS
Temperature qualification voltage input for battery pack negative temperature coefficient thermistor. Program the hot and cold
temperature window with a resistor divider from VREF to TS to GND.
7
TTC
SafetyTimer and termination control. Connect a capacitor from this node to GND to set the timer. When this input is LOW, the timer
and termination are disabled. When this input is HIGH, the timer is disabled but termination is allowed.
8
PG
Open-drain power-good status output. Active LOW when IC has a valid VCC (not in UVLO or ACOV or SLEEP mode). Active HIGH
when IC has an invalid VCC. PGcan be used to drive a LED or communicate with a host processor.
9
STAT2
Open-drain charge status pin to indicate various charger operation.
10
VREF
3.3V regulated voltage output. Place a 1-mF ceramic capacitor from VREF to GND pin close to the IC. This voltage could be used for
programming of voltage and current regulation and for programming the TS threshold.
11
ISET1
Fast Charge current set input. The voltage of ISET1 pin programs the fast charge current regulation set-point.
12
VFB
Output voltage analog feedback adjustment. Connect the output of a resistive voltage divider from the battery terminals to this node to
adjust the output battery regulation voltage.
13
SRN
Charge current sense resistor, negative input. A 0.1-mF ceramic capacitor is placed from SRN to SRP to provide differential-mode
filtering. An optional 0.1-mF ceramic capacitor is placed from SRN pin to GND for common-mode filtering.
14
SRP
Charge current sense resistor, positive input. A 0.1-mF ceramic capacitor is placed from SRN to SRP to provide differential-mode
filtering. A 0.1-mF ceramic capacitor is placed from SRP pin to GND for common-mode filtering.
15
ISET2
Termination current set input. The voltage of ISET2 pin programs termination current trigger point.
16
ACSET
Adapter current set input. The voltage of ACSET pin programs the input current regulation set-point during Dynamic Power
Management (DPM)
17
GND
Low-current sensitive analog/digital ground. On PCB layout, connect with PowerPad underneath the IC.
18
REGN
PWM low side driver positive 6V supply output. Connect a 1-mF ceramic capacitor from REGN to GND pin, close to the IC. Use for
low side driver and high-side driver bootstrap voltage by connecting a small signal Schottky diode from REGN to BTST.
19
LODRV
PWM low side driver output. Connect to the gate of the low-side power MOSFET with a short trace.
20
PH
PWM high side driver negative supply. Connect to the Phase switching node (junction of the low-side power MOSFET drain, high-side
power MOSFET source, and output inductor). Connect the 0.1-mF bootstrap capacitor from PH to BTST.
21
HIDRV
PWM high side driver output. Connect to the gate of the high-side power MOSFET with a short trace.
22
BTST
PWM high side driver positive supply. Connect to the Phase switching node (junction of the low-side power MOSFET drain, high-side
power MOSFET source, and output inductor). Connect the 0.1-mF bootstrap capacitor from SW to BTST.
23
BATDRV
Battery to system MOSFET driver output. Gate drive for the battery to system load BAT PMOS power FET to isolate the system from
the battery to prevent current flow from the system to the battery, while allowing a low impedance path from battery to system.
Connect this pin through a 1-k
resistor to the gate of the input BAT P-channel MOSFET. Connect the source of the FET to the
system load voltage node. Connect the drain of the FET to the battery pack positive terminal. The internal gate drive is asymmetrical
to allow a quick turn-off and slow turn-on, in addition to the internal break-before-make logic with respect to ACDRV. If needed, an
optional capacitor from gate to source of the BATFET is used to slow down the ON and OFF times.
24
VCC
IC power positive supply. Connect through a 10-
to the common-source (diode-OR) point: source of high-side P-channel MOSFET
and source of reverse-blocking power P-channel MOSFET. Place a 1-mF ceramic capacitor from VCC to GND pin close to the IC.
PowerPAD
Exposed pad beneath the IC. Always solder PowerPAD to the board, and have vias on the PowerPAD plane star-connecting to GND
and ground plane for high-current power converter. It also serves as a thermal pad to dissipate the heat.
Copyright 2010, Texas Instruments Incorporated
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