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參數(shù)資料
| 型號： | BP87C51FB |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 12 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 2/18頁 |
| 文件大?。?/td> | 1527K |
| 代理商： | BP87C51FB |
AUTOMOTIVE 87C51FA/FB/FC/FC-20
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first char-
acter is always a `T' (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.
A: Address
C: Clock
D: Input Data
H: Logic level HIGH
I: Instruction (program memory contents)
L: Logic level LOW, or ALE
P: PSEN
Q: Output Data
R: RD signal
T: Time
V: Valid
W: WR signal
X: No longer a valid logic level
Z: Float
For example,
TAVLL e Time from Address Valid to ALE Low
TLLPL e Time from ALE Low to PSEN Low
AC CHARACTERISTICS
(TA eb40 Cto a125 C, VCC e 5V g 20%, VSS e 0V, Load Capacitance
for Port 0, ALE/PROG and PSEN e 100 pF, Load Capacitance for All Other Outputs e 80 pF)
ADVANCED INFORMATION-CONTACT INTEL FOR DESIGN-IN INFORMATION
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
Symbol
Parameter
12 MHz
Variable Oscillator
Units
Oscillator
Min
Max
87C51FA/FB/FC
/ 87C51FC-20
Min
Max
1/T CLCL
Oscillator Frequency
3.5
16/20
MHz
TLHLL
ALE Pulse Width
127
2TCLCL b 40
ns
TAVLL
Address Valid to ALE Low
43
TCLCL b 40
ns
TLLAX
Address Hold After ALE Low
53
TCLCL b 30
ns
TLLIV
ALE Low to Valid
234
4TCLCL b 100/
ns
Instruction In
4TCLCL b 75
TLLPL
ALE Low to PSEN Low
53
TCLCL b 30
ns
TPLPH
PSEN Pulse Width
205
3TCLCL b 45
ns
TPLIV
PSEN Low to Valid
145
3TCLCL b 105/
ns
Instruction In
3TCLCL b 90
TPXIX
Input Inst. Hold After
0
ns
PSEN Trans
TPXIZ
Input Inst. Float After
59
TCLCL b 25/
ns
PSEN Trans
TCLCL b 20
TAVIV
Address Valid to Valid
312
5TCLCL b 105
ns
Instruction In
TPLAZ
PSEN Low to Address
10
ns
Float
TRLRH
RD Pulse Width
400
6TCLCL b 100
ns
TWLWH
WR Pulse Width
400
6TCLCL b 100
ns
10
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