參數(shù)資料
型號(hào): BLV7002
廠商: 上海貝嶺股份有限公司
英文描述: BLV7002
中文描述: BLV7002
文件頁(yè)數(shù): 1/2頁(yè)
文件大?。?/td> 115K
代理商: BLV7002
BLV7002
http://www.belling.com.cn
- 1 -
8/18/2006
Total
2 Pages
BLV7002 N-channel Enhancement Mode
Vertical D-MOS Transistor Chip
Description
N-channel enhancement mode field-effect transistor
Features
Very fast switching
Logic level compatible
Applications
Relay driver
High speed line driver
Logic level translator.
Size
structure
Planar type
Electrodes: Aluminum alloy
Backside metal: Au alloy
Chip size: 495
μ
m ×490
μ
m
Chip thickness: 220±20
μ
m.
Scribe street width: 50
μ
m
Pad size: 90
μ
m x90
μ
m
Die per wafer: 25800
ABSOLUTE MAXIMUM RATING
Symbol
V
DS
V
GS
I
D
I
DM
P
tot
T
STG
T
j
Parameter
Min.
-
-
-
-
-
-55
-
Max.
60
±
20
115
0.46
0.2
+150
150
Unit
V
V
mA
A
W
o
C
o
C
Drain – source voltage (DC)
Gate – source voltage (DC)
Drain current (DC)
Peak drain current
Total power dissipation
Storage temperature
Junction temperature
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