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參數(shù)資料
| 型號： | BH16899DL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | 18-bit latched transceiver with 16-bit parity generator/checker 3-State |
| 中文描述： | ABT SERIES, 16-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 7.50 MM, PLASTIC, MO-118AB, SOT-371-1, SSOP-56 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 105K |
| 代理商： | BH16899DL |
Philips Semiconductors
Product specification
74ABT16899
74ABTH16899
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
1998 Feb 25
5
BLOCK DIAGRAM
1
mux
0
9–bit
Output
Buffer
OE
9–bit
Output
Buffer
9–bit
Transparent
Latch
LE
Parity
Generator
Parity
Generator
1
0
mux
OE
9–bit
Transparent
Latch
LE
OEB
LEA
A0
A1
A2
A3
A4
A5
A6
A7
APAR
OEA
SEL
ODD/
EVEN
LEB
B7
BPAR
B6
B5
B4
B3
B2
B1
B0
ERRA
ERRB
SH00084
(1 of 2 parity blocks)
FUNCTION TABLE
INPUTS
OPERATING MODE
OEB
OEA
SEL
LEA
LEB
H
H
X
X
X
3-State A bus and B bus (input A & B simultaneously)
H
L
L
L
H
B
→
A, transparent B latch, generate parity from B0 - B7, check B bus parity
B
→
A, transparent A & B latch, generate parity from B0 - B7, check A & B bus parity
B
→
A, B bus latched, generate parity from latched B0 - B7 data, check B bus parity
B
→
A, transparent B latch, parity feed-through, check B bus parity
H
L
L
H
H
H
L
L
X
L
H
L
H
X
H
H
L
H
H
H
B
→
A, transparent A & B latch, parity feed-through, check A & B bus parity
A
→
B, transparent A latch, generate parity from A0 - A7, check A bus parity
A
→
B, transparent A & B latch, generate parity from A0 - A7, check A & B bus parity
A
→
B, A bus latched, generate parity from latched A0 - A7 data, check A bus parity
A
→
B, transparent A latch, parity feed-through, check A bus parity
A
→
B, transparent A & B latch, parity feed-through, check A & B bus parity
L
H
L
H
X
L
H
L
H
H
L
H
L
L
X
L
H
H
H
L
L
H
H
H
H
L
L
X
X
X
Output to A bus and B bus (NOT ALLOWED)
H =
L
X =
High voltage level
Low voltage level
Don’t care
=
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