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參數(shù)資料
| 型號： | BH16646DL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | 16-bit bus transceiver/register 3-State |
| 中文描述： | ABT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | PLASTIC, SSOP3-56 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 94K |
| 代理商： | BH16646DL |
Philips Semiconductors
Product specification
74ABT16646
74ABTH16646
16-bit bus transceiver/register (3-State)
1998 Feb 27
7
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
MIN
MAX
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
t/
v
DC supply voltage
4.5
5.5
V
Input voltage
0
V
CC
V
High-level input voltage
2.0
V
Low-level Input voltage
0.8
V
High-level output current
–32
mA
Low-level output current
64
mA
Input transition rise or fall rate
0
10
ns/V
T
amb
Operating free-air temperature range
–40
+85
°
C
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25
°
C
T
amb
= –40
°
C
to +85
°
C
MIN
UNIT
MIN
TYP
–0.9
2.9
3.4
2.4
0.35
0.13
MAX
–1.2
MAX
–1.2
V
IK
Input clamp voltage
V
CC
= 4.5V; I
IK
= –18mA
V
CC
= 4.5V; I
OH
= –3mA; V
I
= V
IL
or V
IH
V
CC
= 5.0V; I
OH
= –3mA; V
I
= V
IL
or V
IH
V
CC
= 4.5V; I
OH
= –32mA; V
I
= V
IL
or V
IH
V
CC
= 4.5V; I
OL
= 64mA; V
I
= V
IL
or V
IH
V
CC
= 5.5V; I
O
= 1mA; V
I
= GND or V
CC
V
V
V
V
V
V
2.5
3.0
2.0
2.5
3.0
2.0
V
OH
High-level output voltage
V
OL
V
RST
Low-level output voltage
Power-up output voltage
3
0.55
0.55
0.55
0.55
I
I
Input leakag
current
= 5 5V; V
= GND or 5 5V
V
CC
= 5.5V V
I
= GND or 5.5V
Control
pins
0 01
±
0.01
1 0
±
1.0
1 0
±
1.0
μ
A
Bus Hold current A or B
Ports 74ABTH16646
V
CC
= 4.5V; V
I
= 0.8V
V
CC
= 4.5V; V
I
= 2.0V
V
CC
= 5.5V; V
I
= 0 to 5.5V
V
CC
= 0.0V; V
O
= 4.5V; V
I
= 0.0V or 5.5V
V
CC
= 2.1V; V
O
= 0.0V or V
;
V
I
CC
; OE/OE = X
V
CC
= 5.5V; V
O
= 5.5V; V
I
= V
IL
or V
IH
V
CC
= 5.5V; V
O
= 0.0V; V
I
= V
IL
or V
IH
35
–75
±
800
35
–75
I
HOLD
μ
A
I
OFF
Power-off leakage current
Power-up/down 3-State
output current
4
3-State output High current
3-State output Low current
Output High leakage
current
Output current
1
±
2.0
±
100
±
100
μ
A
I
PU/PD
±
1.0
±
50
±
50
μ
A
I
IH
+ I
OZH
I
IL
+ I
OZL
1.0
–1.0
10
–10
10
–10
μ
A
μ
A
I
CEX
V
CC
= 5.5V; V
O
= 5.5V; V
I
= GND or V
CC
5.0
50
50
μ
A
I
O
V
CC
= 5.5V; V
O
= 2.5V
V
CC
= 5.5V; Outputs High, V
I
= GND or
V
CC
V
CC
= 5.5V; Outputs Low, V
I
= GND or V
CC
V
CC
= 5.5V; Outputs 3–State;
V
I
= GND or V
CC
–50
–80
–180
–50
–180
mA
I
CCH
0.55
2
2
mA
I
CCL
Quiescent supply current
9
19
19
mA
I
CCZ
0.55
2
2
mA
I
CC
Additional supply current
per input pin
2
74ABT16646
V
= 5.5V; one input at 3.4V,
other inputs at V
CC
or GND
5.0
50
50
μ
A
I
CC
Additional supply current
per input pin
2
74ABTH16646
V
= 5.5V; one input at 3.4V,
other inputs at V
CC
or GND
200
500
500
μ
A
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V
between 0V and 2.0V, with a transition time of up to 100msec. From V
CC
= 21.V to V
CC
= 5V
±
10% a
transition time of up to 100
μ
sec is permitted.
5. This is the bus hold overdrive current required to force the input to the opposite logic state.
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