參數(shù)資料
型號： BH161543DGG
廠商： NXP SEMICONDUCTORS
元件分類： 通用總線功能
英文描述： 16-bit latched transceiver with dual enable and master reset 3-State
中文描述： ABT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
封裝： PLASTIC, TSSOP2-56
文件頁數(shù)： 7/12頁
文件大?。?/td> 85K
代理商： BH161543DGG
Philips Semiconductors
Product specification
74ABT161543
74ABTH161543
16-bit latched transceiver with dual enable
and master reset (3-State)
1998 Feb 27
7
AC CHARACTERISTICS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500
LIMITS
SYMBOL
PARAMETER
WAVEFORM
T
amb
= +25
o
C
V
CC
= +5.0V
T
amb
= –40 to +85
o
C
V
CC
= +5.0V
±
0.5V
UNIT
MIN
TYP
MAX
MIN
MAX
t
PLH
t
PHL
Propagation delay
nAx to nBx, nBx to nAx
2
1.2
1.0
2.5
2.2
3.4
2.9
1.2
1.0
3.9
3.5
ns
t
PLH
t
PHL
Propagation delay
LEBA to nAx, LEAB to nBx
1
2
1.2
1.2
3.0
2.6
4.1
3.5
1.2
1.2
5.1
4.1
ns
t
PHL
MRba to nAx, MRab to nBx
6
1.2
2.6
3.4
1.2
4.2
ns
t
PZH
t
PZL
Output enable time
OEBA to nAx, OEAB to nBx
4
5
1.4
1.4
3.3
3.4
4.4
4.4
1.4
1.4
5.5
5.6
ns
t
PHZ
t
PLZ
Output disable time
OEBA to nAx, OEAB to nBx
4
5
1.4
1.4
3.5
2.7
4.8
3.5
1.4
1.4
5.4
4.0
ns
t
PZH
t
PZL
Output enable time
EBA to nAx, EAB to nBx
4
5
1.4
1.4
3.4
3.5
4.4
4.4
1.4
1.4
5.6
5.7
ns
t
PHZ
t
PLZ
Output disable time
EBA to nAx, EAB to nBx
4
5
1.3
1.3
3.5
2.7
4.4
3.5
1.3
1.3
5.4
4.0
ns
AC SETUP REQUIREMENTS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500
LIMITS
SYMBOL
PARAMETER
WAVEFORM
T
amb
= +25
o
C
V
CC
= +5.0V
T
amb
= –40 to +85
o
C
V
CC
= +5.0V
±
0.5V
UNIT
MIN
TYP
MIN
t
s
(H)
t
s
(L)
Setup time
nAx to LEAB, nBx to LEBA
3
1.5
2.0
–0.3
0.1
1.5
2.0
ns
t
h
(H)
t
h
(L)
Hold time
nAx to LEAB, nBx to LEBA
3
1.5
2.0
–0.1
0.1
1.5
2.0
ns
t
s
(H)
t
s
(L)
Setup time
nAx to EAB, nBx to EBA
3
1.5
2.0
–0.1
0.2
1.5
2.0
ns
t
h
(H)
t
h
(L)
Hold time
nAx to EAB, nBx to EBA
3
1.5
2.0
–0.1
–0.1
1.5
2.0
ns
t
w
(L)
Latch enable pulse width, Low
3
4.0
2.0
4.0
ns
t
w
(L)
MR Pulse width, Low
6
3.0
1.0
3.0
ns
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