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參數(shù)資料
| 型號： | BD00HA5WEFJ-E2 |
| 元件分類： | 可調(diào)正電壓單路輸出LDO穩(wěn)壓器 |
| 英文描述： | ADJUSTABLE POSITIVE LDO REGULATOR, PDSO8 |
| 封裝： | ROHS COMPLIANT, HTSOP-8 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 416K |
| 代理商： | BD00HA5WEFJ-E2 |
www.rohm.com
2010.10 - Rev.A
2010 ROHM Co., Ltd. All rights reserved.
Technical Note
10/11
BD00IA5WEFJ
(11) Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.
A lways discharge capacitors after each process or step. Always turn the IC’s power supply off before connecting it to or
removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic
measure. Use similar precaution when transporting or storing the IC.
(12) Regarding input pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode
or transistor. For example, the relation between each potential is as follows:
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes
operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used.
(13) Ground Wiring Pattern.
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns,
placing a single ground point at the ground potential of application so that the pattern wiring resistance and voltage
variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the
GND wiring pattern of any external components, either.
Resistor
Transistor (NPN)
N
N P+
P
+
P
P substrate
GND
Parasitic element
Pin A
N
P
+
P
+
P
P substrate
GND
Parasitic element
Pin B
C
B
E
N
GND
Pin A
Parasitic
element
Pin B
Other adjacent elements
E
B
C
GND
Parasitic
element
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