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參數(shù)資料
| 型號： | BA823F-E2 |
| 廠商： | Rohm Semiconductor |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DRIVER SER/PAR I/O 8BIT SOP16 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 驅(qū)動器 |
| 驅(qū)動器/接收器數(shù)： | 8/0 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 1369 (CN2011-ZH PDF) |
| 其它名稱： | BA823F-E2DKR |
BA823F
Technical Note
3/8
www.rohm.com
2009.06 - Rev.A
2009 ROHM Co., Ltd. All rights reserved.
●Block diagram
●Pin descriptions
Pin No.
Pin Name
Symbol
Function
2
SHIFT PULSE
C
Shift pulse of shift register
15
DATA INPUT
D1
Data input of shift register is stored during the shift pulse rise time.
1
STROBE
S
When “1” is effective, the content of shift register is outputted.
12
OUTPUT
0
“0” is effective when the content of register is “1” on the 1st bit is outputted.
11
OUTPUT
1
“0” is effective when the content of register is “1” on the 2nd bit is outputted.
10
OUTPUT
2
“0” is effective when the content of register is “1” on the 3rd bit is outputted.
9
OUTPUT
3
“0” is effective when the content of register is “1” on the 4th bit is outputted.
8
OUTPUT
4
“0” is effective when the content of register is “1” on the 5th bit is outputted.
7
OUTPUT
5
“0” is effective when the content of register is “1” on the 6tht bit is outputted.
6
OUTPUT
6
“0” is effective when the content of register is “1” on the 7tht bit is outputted.
5
OUTPUT
7
“0” is effective when the content of register is “1” on the 8th bit is outputted.
3
DATA OUTPUT
Do
Data having passed through the output circuit of
7 becomes the input of the next stage
16
VCC
5.0V .is used normally (±10%)
13
GND
GND1
Especially, GND of the output circuit of
0~ 3
4
GND
GND2
Especially, GND of the output circuit of
4~ 7
14
GND
GND(Dig)
Especially, GND of the logic circuit
●Description of operation
BA823 is configured internally as shown in the block diagram. Terminals of clock C, data D1, and strobe S are used as input.
Data input is synchronized with the clock, read serially during the rise time and latched at the rise time edge of the shifted
shift register. The content of the set shift register appears on the output terminal of
0~ 7 when the strobe is input, as
shown in the time chart of Fig.5. Pulse width is the same as that of the strobe input pulse.
Data output terminal D0, is a terminal used for cascade connection of the IC, where the output of the final stage of the shift
register has appeared, and is connected to the next data input terminal D1. In this case, when the clock and the strobe are
used in conjunction, output terminal can be increased by 8 bits at a time.
1
15
2
16
3
13
4
14
12
11
10
9
8
7
6
5
DATA OUTPUT
DO
GND1
GND2
GND
(Dig)
VCC
STROBE INPUT
S
DATA INPUT
D4
SHIFT PULSE
C
0
1
2
3
4
5
6
7
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