參數(shù)資料
型號: B900M24PXX12T
元件分類: 數(shù)字信號處理
英文描述: 0-BIT, 59.88 MHz, OTHER DSP, PQCC44
文件頁數(shù): 75/100頁
文件大小: 1547K
代理商: B900M24PXX12T
76
Lucent Technologies Inc.
B900
Advance Data Sheet
Baseband Signal Processor
July 1999
7 Electrical Requirements and Characteristics (continued)
7.2
Input and I/O Buffer Power Dissipation
Power dissipation due to the input and I/O buffers is highly dependent on the input voltage level. At full CMOS
levels, essentially no dc current is drawn. However, for levels near the threshold of 1.4 V, high current can flow.
Therefore, all unused input pins should be tied inactive to VDD or VSS, and all unused I/O pins should be tied inac-
tive through the pull-up or pull-down options.
Tables 96 and 97 show the input buffer power dissipation for 29 inputs biased at dc level, VIN, with VDD at 5.0 V.
Warning: The device needs to be clocked for at least 12 fXTALB cycles during reset after powerup;
otherwise, high current may flow.
Table 96. Input Buffer Maximum Power Dissipation
VIN (V)
5.0
3.6
2.8
2.4
2.0
1.4
0.8
0.4
0
PD (mW) <1.0
13.5
140
180
High
80
7.5
<1.0
Table 97. Schmitt Trigger Input Buffer Maximum Power Dissipation
VIN (V)
5.0
3.6
2.8
2.4
2.0
1.4
0.8
0.4
0
PD (mW) <1.0
13.5
140
180
80
7.5
<1.0
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