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參數(shù)資料
| 型號： | B250W48A106XXG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 13/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR AUDIO 16BIT 48WLCSP |
| 標準包裝： | 2,500 |
| 系列： | BelaSigna® 250 |
| 類型： | 音頻處理器 |
| 應用： | 便攜式設備 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFBGA，WLCSP |
| 供應商設備封裝： | 48-WLCSP（3.8x2.58） |
| 包裝： | 帶卷 (TR) |
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BELASIGNA 250
http://onsemi.com
20
Table 9. INTERRUPT DESCRIPTIONS
Interrupt
Description
WOLA_DONE
WOLA function done
IO_BLOCK_FULL
IOP interrupt
GP_TIMER
Generalpurpose timer interrupt
WATCHDOG_TIMER
Watchdog timer interrupt
SPI_INTERFACE
SPI interface interrupt
IR
IR remote interrupt
EXT3_RX
EXT3 register receive interrupt
EXT3_TX
EXT3 register transmit interrupt
GPIO
User configurable GPIO interrupt
TWSS_INTERFACE
Twowire synchronous serial interface interrupt
UART_RX
Generalpurpose UART receive interrupt
UART_TX
Generalpurpose UART transmit interrupt
PCM
PCM interface interrupt
Analog Blocks
Input Stage
The analog audio input stage is comprised of two
individual channels. For each channel, the selected one out
of the four possible inputs is routed to the input of the
programmable preamplifier that can be configured for
bypass or gain values of 12 to 30 dB (3 dB steps).
The analog signal is filtered to remove frequencies above
20 kHz before it is passed into the highfidelity 16bit
oversampling
SD A/D converter. Subsequently, any
necessary sample rate decimation is performed to
downsample the signal to the desired sampling rate. During
decimation the level of the signal can be adjusted digitally
for optimal gain matching between the two input channels.
Any undesired DC component can be removed by a
configurable DCremoval filter that is part of the
decimation circuitry. The DC removal filter can be
configured for bypass or cutoff frequencies at 5, 10 and
20 Hz.
A builtin feature allows a sampling delay to be
configured between channel zero and channel one (or vice
versa). This is useful in beamforming applications.
Note: Both preamplifiers can be daisychained to increase
the potential gain, but the signal has to be routed externally
to the chip.
For power consumption savings either of the input
channels can be disabled via software. A different input
must be selected for each channel. The input stage is shown
in Figure 7.
Figure 7. Input Stage
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