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參數(shù)資料
| 型號(hào)： | AZ7033ZTR-E1 |
| 廠商： | BCD SEMICONDUCTOR MANUFACTURING LTD |
| 元件分類： | 電源管理 |
| 英文描述： | VOLTAGE DETECTOR |
| 中文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PBCY3 |
| 封裝： | ROHS COMPLIANT, TO-92, 3PIN |
| 文件頁(yè)數(shù)： | 9/13頁(yè) |
| 文件大小： | 172K |
| 代理商： | AZ7033ZTR-E1 |
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9
Mar. 2007 Rev. 1. 5
BCD Semiconductor Manufacturing Limited
VOLTAGE DETECTOR AZ70XX
Preliminary Datasheet
Figure 13. Low Voltage Indicator
Figure 14. CPU Resetting Circuit
1
3
2
V
CC
AZ70XX
OUT
GND
LED
V
CC
R1
220
V
CC
+5V
R1
3.3k
1
3
2
V
CC
AZ70XX
OUT
GND
CPU
V
CC
GND
RESET
C1
1
μ
F
+
Operating Diagram (Continued)
Typical Applications
Figure 12 is a typical timing waveform for AZ70XX.
In normal steady-state operation when V
CC
>V
DET-
,
the
output will be in a logic high state and V
OUT
is
dependent upon the voltage that the pull-up resistor
connected to.
Here is some explanations for AZ70XX's operation.
1.
When the input voltage V
CC
falls below V
DET-
, the
output will pull down to logic low after a delay time of
tpHL. In general, at rated output current and V
CC
,
V
OUT
can be pulled down to a voltage as low as within
0.4V from GND. (See the Electrical Characteristics
section). The voltage level V
DET-
means the detect
voltage.
2.
The output, V
OUT
, will stay valid until V
CC
falls
below the minimum operating voltage, V
OPR
(0.8V
typical). Below minimum operating voltage, the out-
put is undefined.
3.
During power-up, V
OUT
will remain undefined until
V
CC
rises above V
OPR
, at which time the output will
become valid. V
OUT
will be in its active low state
while
V
OPR
<
V
CC
<
V
DET+
(V
DET+
=V
DET-
+V
HYS
).
V
DET+
is the release voltage. V
HYS
means the hystere-
sis voltage and is the difference voltage between the
V
DET+
and V
DET-
.
4.
When V
CC
rises above V
DET+
, the output will be in
its inactive state. After a delay time of tpLH, V
OUT
will be in its logic high state .
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