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參數(shù)資料
| 型號： | AXDA1900DLT3D |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 37/104頁 |
| 文件大?。?/td> | 1769K |
| 代理商： | AXDA1900DLT3D |
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Chapter 6
Advanced 266 Front-Side Bus AMD Athlon XP Processor Model 8 Specifications
25
25175E—November 2002
AMD Athlon XP Processor Model 8 Data Sheet
Preliminary Information
6.3
Advanced 266 FSB AMD Athlon System Bus
AC Characteristics
The AC characteristics for the AMD Athlon system bus of this
processor are shown in Table 4. The parameters are grouped
based on the source or destination of the signals involved.
Table 4.
AMD Athlon System Bus AC Characteristics
Group
Symbol
Parameter
Min
1
Max
3
Units
V/ns
Notes
1
All Signals
T
RISE
T
FALL
Output Rise Slew Rate
Output Fall Slew Rate
Output skew with respect to
the same clock edge
Output skew with respect to a
different clock edge
Input Data Setup Time
1
3
V/ns
1
Forward
Clocks
T
SKEW-SAMEEDGE
–
385
ps
2
T
SKEW-DIFFEDGE
–
770
ps
2
T
SU
T
HD
C
IN
C
OUT
T
VAL
T
SU
T
HD
300
ps
3
Input Data Hold Time
300
ps
3
Capacitance on input Clocks
4
25
pF
Capacitance on output Clocks
4
12
pF
Sync
RSTCLK to Output Valid
250
2000
ps
4, 5
Setup to RSTCLK
500
ps
4, 6
Hold from RSTCLK
1000
ps
4, 6
Notes:
1. Rise and fall time ranges are guidelines over which the I/O has been characterized.
2. T
SKEW-SAMEEDGE
is the maximum skew within a clock forwarded group between any two signals or between any signal and its
forward clock, as measured at the package, with respect to the same clock edge.
T
SKEW-DIFFEDGE
is the maximum skew within a clock forwarded group between any two signals or between any signal and its
forward clock, as measured at the package, with respect to different clock edges.
3. Input SU and HD times are with respect to the appropriate Clock Forward Group input clock.
4. The synchronous signals include
PROCRDY, CONNECT, and CLKFWDRST.
5. T
VAL
is RSTCLK rising edge to output valid for PROCRDY. Test Load is 25 pF.
6. T
SU
is setup of CONNECT/CLKFWDRST to rising edge of RSTCLK. T
HD
is hold of CONNECT/CLKFWDRST from rising edge of
RSTCLK.
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