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參數(shù)資料
| 型號(hào)： | AXDA1800DUT3C |
| 元件分類(lèi)： | 微處理器 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁(yè)數(shù)： | 85/104頁(yè) |
| 文件大?。?/td> | 1769K |
| 代理商： | AXDA1800DUT3C |
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Chapter 11
Pin Descriptions
73
25175E—November 2002
AMD Athlon XP Processor Model 8 Data Sheet
Preliminary Information
FID[3:0] Pins
FID[3] (Y3), FID[2] (Y1), FID[1] (W3), and FID[0] (W1) are the
4-bit processor clock-to-SYSCLK ratio.
Table 25 describes the encodings of the clock multipliers on
FID[3:0].
The FID[3:0] signals are open-drain processor outputs that are
pulled High on the motherboard and sampled by the chipset to
determine the SIP (Serialization Initialization Packet) that is
sent to the processor. The FID[3:0] signals are valid after
PWROK is asserted. The FID[3:0]signals must not be sampled
until they become valid. See the
AMD Athlon System Bus
Specification
, order# 21902 for more information about
Serialization Initialization Packets and SIP protocol.
The processor FID[3:0] outputs are open-drain and 2.5 V
tolerant. To prevent damage to the processor, if these signals
are pulled High to above 2.5 V, they must be electrically
isolated from the processor. For information about the FID[3:0]
Table 25. FID[3:0] Clock Multiplier Encodings
FID[3:0]
2
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Processor Clock to SYSCLK Frequency Ratio
11
11.5
12
≥
12.5
1
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5
10
10.5
Notes:
1. All ratios greater than or equal to 12.5x have the same FID[3:0] code of 0011b, which causes
the SIP configuration for all ratios of 12.5x or greater to be the same.
2. BIOS initializes the CLK_Ctl MSR during the POST routine. This CLK_Ctl setting is used with all
FID combinations and selects a Halt disconnect divisor and a Stop Grant disconnect divisor.
For more information, refer to the
AMD Athlon and AMD Duron Processors BIOS,
Software, and Debug Developers Guide
, order# 21656.
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