- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362556 > AXDA1800DLV3C Microprocessor PDF資料下載
參數(shù)資料
| 型號(hào)： | AXDA1800DLV3C |
| 元件分類： | 微處理器 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁(yè)數(shù)： | 37/104頁(yè) |
| 文件大小： | 1769K |
| 代理商： | AXDA1800DLV3C |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)當(dāng)前第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)
Chapter 6
Advanced 266 Front-Side Bus AMD Athlon XP Processor Model 8 Specifications
25
25175E—November 2002
AMD Athlon XP Processor Model 8 Data Sheet
Preliminary Information
6.3
Advanced 266 FSB AMD Athlon System Bus
AC Characteristics
The AC characteristics for the AMD Athlon system bus of this
processor are shown in Table 4. The parameters are grouped
based on the source or destination of the signals involved.
Table 4.
AMD Athlon System Bus AC Characteristics
Group
Symbol
Parameter
Min
1
Max
3
Units
V/ns
Notes
1
All Signals
T
RISE
T
FALL
Output Rise Slew Rate
Output Fall Slew Rate
Output skew with respect to
the same clock edge
Output skew with respect to a
different clock edge
Input Data Setup Time
1
3
V/ns
1
Forward
Clocks
T
SKEW-SAMEEDGE
–
385
ps
2
T
SKEW-DIFFEDGE
–
770
ps
2
T
SU
T
HD
C
IN
C
OUT
T
VAL
T
SU
T
HD
300
ps
3
Input Data Hold Time
300
ps
3
Capacitance on input Clocks
4
25
pF
Capacitance on output Clocks
4
12
pF
Sync
RSTCLK to Output Valid
250
2000
ps
4, 5
Setup to RSTCLK
500
ps
4, 6
Hold from RSTCLK
1000
ps
4, 6
Notes:
1. Rise and fall time ranges are guidelines over which the I/O has been characterized.
2. T
SKEW-SAMEEDGE
is the maximum skew within a clock forwarded group between any two signals or between any signal and its
forward clock, as measured at the package, with respect to the same clock edge.
T
SKEW-DIFFEDGE
is the maximum skew within a clock forwarded group between any two signals or between any signal and its
forward clock, as measured at the package, with respect to different clock edges.
3. Input SU and HD times are with respect to the appropriate Clock Forward Group input clock.
4. The synchronous signals include
PROCRDY, CONNECT, and CLKFWDRST.
5. T
VAL
is RSTCLK rising edge to output valid for PROCRDY. Test Load is 25 pF.
6. T
SU
is setup of CONNECT/CLKFWDRST to rising edge of RSTCLK. T
HD
is hold of CONNECT/CLKFWDRST from rising edge of
RSTCLK.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AXDA1800DUT3C | Microprocessor |
| AXDA1800DUV3C | Microprocessor |
| AXDA1900DKT3C | Microprocessor |
| AXDA1900DKV3C | Microprocessor |
| AXDA1900DLT3C | Microprocessor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AXDA2800DKV4D | 制造商:Advanced Micro Devices 功能描述:MPU AMD Athlon XP 64-Bit 0.13um 2.083GHz 453-Pin OPGA |
| AXDBG-2-GEVK | 功能描述:AX8052F1 - Debugger 制造商:on semiconductor 系列:- 零件狀態(tài):有效 類型:調(diào)試程序 配套使用產(chǎn)品/相關(guān)產(chǎn)品:AX8052F1 內(nèi)容:板 標(biāo)準(zhǔn)包裝:1 |
| AXE | 制造商:Velleman Inc 功能描述: |
| AXE.25A | 制造商:Distributed By MCM 功能描述:AGX 1'' x 1/4'' |
| AXE10 | 制造商:AXTAL 制造商全稱:AXTAL 功能描述:SMD PXO (Clock) in CO 26 package |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。