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| 型號(hào)： | AXDA1800DLT3D |
| 英文描述： | Metal Film Resistor - RN 1/8 T9 82.5K 1% A |
| 中文描述： | 微處理器 |
| 文件頁(yè)數(shù)： | 52/104頁(yè) |
| 文件大小： | 1769K |
| 代理商： | AXDA1800DLT3D |
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40
Electrical Data
Chapter 8
AMD Athlon XP Processor Model 8 Data Sheet
25175E—November 2002
Preliminary Information
T
BIT
T
RPT
T
RISE
T
FALL
C
P
IN
T
VALID
Notes:
Input Time to Acquire
20.0
ns
7, 8
Input Time to Reacquire
40.0
ns
9–13
Signal Rise Time
1.0
3.0
V/ns
6
Signal Fall Time
1.0
3.0
V/ns
6
Pin Capacitance
4
12
pF
Time to data valid
100
ns
14
Table 16. General AC and DC Characteristics (continued)
Symbol
Parameter Description
Condition
Min
Max
Units
Notes
1. Characterized across DC supply voltage range.
2. Values specified at nominal V
CC_CORE
. Scale parameters between V
CC_CORE.
minimum and V
CC_CORE.
maximum.
3. I
OL
and I
OH
are measured at V
OL
maximum and V
OH
minimum, respectively.
4. Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins.
5. These are aggregate numbers.
6. Edge rates indicate the range over which inputs were characterized.
7.
In asynchronous operation, the signal must persist for this time to enable capture.
8. This value assumes RSTCLK period is 10 ns ==> TBIT = 2*fRST.
9. The approximate value for standard case in normal mode operation.
10. This value is dependent on RSTCLK frequency, divisors, Low Power mode, and core frequency.
11. Reassertions of the signal within this time are not guaranteed to be seen by the core.
12. This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase.
13. This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other
configurations.
14. Time to valid is for any open-drain pins. See requirements 7 and 8 in the “Power-Up Timing Requirements“ Chapter for more
information.
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