- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362556 > AXDA1700DLT3D Microprocessor PDF資料下載
參數(shù)資料
| 型號： | AXDA1700DLT3D |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 59/104頁 |
| 文件大?。?/td> | 1769K |
| 代理商： | AXDA1700DLT3D |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁當前第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁
Chapter 9
Signal and Power-Up Requirements
47
25175E—November 2002
AMD Athlon XP Processor Model 8 Data Sheet
Preliminary Information
clock must be valid at this time. The system clocks are
designed to be running after 3.3 V has been within
specification for three milliseconds.
4. PWROK assertion to deassertion of RESET#
The duration of RESET# assertion during cold boots is
intended to satisfy the time it takes for the PLL to lock with
a less than 1 ns phase error. The processor PLL begins to
run after PWROK is asserted and the internal clock grid is
switched from the ring oscillator to the PLL. The PLL lock
time may take from hundreds of nanoseconds to tens of
microseconds. It is recommended that the minimum time
between PWROK assertion to the deassertion of RESET# be
at least
1.0 milliseconds
. Southbridges enforce a delay of
1.5 to 2.0 milliseconds between PWRGD (Southbridge
version of PWROK) assertion and NB_RESET# deassertion.
5. PWROK must be monotonic and meet the timing
requirements as defined in Table 16, “General AC and DC
Characteristics,” on page 39. The processor should not
switch between the ring oscillator and the PLL after the
initial assertion of PWROK.
6. NB_RESET# must be asserted (causing CONNECT to also
assert) before RESET# is deasserted. In practice all
Southbridges enforce this requirement.
If NB_RESET# does not assert until after RESET# has
deasserted, the processor misinterprets the CONNECT
assertion (due to NB_RESET# being asserted) as the
beginning of the SIP transfer. There must be sufficient
overlap in the resets to ensure that CONNECT is sampled
asserted by the processor before RESET# is deasserted.
7. The FID[3:0] signals are valid within 100 ns after PWROK is
asserted. The chipset must not sample the FID[3:0] signals
until they become valid. Refer to the
AMD Athlon
Processor-Based Motherboard Design Guide
, order# 24363, for
the specific implementation and additional circuitry
required.
8. The FID[3:0] signals become valid within 100 ns after
RESET# is asserted. Refer to the
AMD Athlon Processor-
Based Motherboard Design Guide
, order# 24363, for the
specific implementation and additional circuitry required.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AXDA1700DLV3C | Microprocessor |
| AXDA1700DUT3C | Microprocessor |
| AXDA1700DUV3C | Microprocessor |
| AXDA1800DKT3C | Microprocessor |
| AXDA1800DKV3C | Microprocessor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AXDA2800DKV4D | 制造商:Advanced Micro Devices 功能描述:MPU AMD Athlon XP 64-Bit 0.13um 2.083GHz 453-Pin OPGA |
| AXDBG-2-GEVK | 功能描述:AX8052F1 - Debugger 制造商:on semiconductor 系列:- 零件狀態(tài):有效 類型:調(diào)試程序 配套使用產(chǎn)品/相關(guān)產(chǎn)品:AX8052F1 內(nèi)容:板 標準包裝:1 |
| AXE | 制造商:Velleman Inc 功能描述: |
| AXE.25A | 制造商:Distributed By MCM 功能描述:AGX 1'' x 1/4'' |
| AXE10 | 制造商:AXTAL 制造商全稱:AXTAL 功能描述:SMD PXO (Clock) in CO 26 package |
發(fā)布緊急采購，3分鐘左右您將得到回復。