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| 型號： | AXDA1700DLT3C |
| 元件分類： | 微處理器 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 58/104頁 |
| 文件大?。?/td> | 1769K |
| 代理商： | AXDA1700DLT3C |
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46
Signal and Power-Up Requirements
Chapter 9
AMD Athlon XP Processor Model 8 Data Sheet
25175E—November 2002
Preliminary Information
Power-Up Timing Requirements.
The signal timing requirements are
as follows:
1. RESET# must be asserted before PWROK is asserted.
The AMD Athlon XP processor model 8 does not set the
correct clock multiplier if PWROK is asserted prior to a
RESET# assertion. It is recommended that RESET# be
asserted at least
10 nanoseconds
prior to the assertion of
PWROK.
In practice, a Southbridge asserts RESET# milliseconds
before PWROK is asserted.
2. All
specification before PWROK is asserted.
PWROK is an output of the voltage regulation circuit on the
motherboard. PWROK indicates that V
CC_CORE
and all
other voltage planes in the system are within specification.
The motherboard is required to delay PWROK assertion for
a minimum of three milliseconds from the 3.3 V supply
being within specification. This delay ensures that the
system clock (SYSCLK/SYSCLK#) is operating within
specification when PWROK is asserted.
The processor core voltage, V
CC_CORE
, must be within
specification as dictated by the VID[4:0] pins driven by the
processor before PWROK is asserted. Before PWROK
assertion, the AMD Athlon processor is clocked by a ring
oscillator.
The processor PLL is powered by VCCA. The processor PLL
does not lock if VCCA is not high enough for the processor
logic to switch for some period before PWROK is asserted.
VCCA must be within specification at least five
microseconds before PWROK is asserted.
In practice VCCA, V
CC_CORE
, and all other voltage planes
must be within specification for several milliseconds before
PWROK is asserted.
After PWROK is asserted, the processor PLL locks to its
operational frequency.
motherboard
voltage
planes
must
be
within
3. The system clock (SYSCLK/SYSCLK#) must be running
before PWROK is asserted.
When PWROK is asserted, the processor switches from
driving the internal processor clock grid from the ring
oscillator to driving from the PLL. The reference system
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| AXDA1700DLT3D | Microprocessor |
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| AXDA1700DUT3C | Microprocessor |
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| AXDA1800DKT3C | Microprocessor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AXDA2800DKV4D | 制造商:Advanced Micro Devices 功能描述:MPU AMD Athlon XP 64-Bit 0.13um 2.083GHz 453-Pin OPGA |
| AXDBG-2-GEVK | 功能描述:AX8052F1 - Debugger 制造商:on semiconductor 系列:- 零件狀態(tài):有效 類型:調(diào)試程序 配套使用產(chǎn)品/相關(guān)產(chǎn)品:AX8052F1 內(nèi)容:板 標(biāo)準(zhǔn)包裝:1 |
| AXE | 制造商:Velleman Inc 功能描述: |
| AXE.25A | 制造商:Distributed By MCM 功能描述:AGX 1'' x 1/4'' |
| AXE10 | 制造商:AXTAL 制造商全稱:AXTAL 功能描述:SMD PXO (Clock) in CO 26 package |
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