
ASIX ELECTRONICS CORPORATION
17
AX88772A/AX88172A
Low-pin-count
USB 2.0 to 10/100M Fast Ethernet Controller
GPIO_1
B5/PD
35
General Purpose Input/ Output Pin 1. This pin is default as input pin after
power-on reset. This pin is also for Default WOL Ready Mode setting;
please refer to section
2.3
Settings.
General Purpose Input/ Output Pin 0 or PME (Power Management Event).
This pin is default as input pin after power-on reset. GPIO_0 also can be
defined as PME output to indicate wake up event detected. Please refer to
section
2.3
Settings.
UART_RX or SPI_MISO. This is a multi-function pin determined by
EEPROM Flag [1] setting. Please refer to section
2.3
Settings.
UART_TX or SPI_MOSI. This is a multi-function pin determined by
EEPROM Flag [1] setting. Please refer to section
2.3
Settings.
I2C_SDA or SPI_SS. This is a multi-function pin determined by
EEPROM Flag [1] setting. Please refer to section
2.3
Settings.
I2C_SCLK or SPI_SCLK. This is a multi-function pin determined by
EEPROM Flag [1] setting. Please refer to section
2.3
Settings.
USB Speed indicator: When USB bus is in Full speed, this pin drives high
continuously. When USB bus is in High speed, this pin drives low
continuously. This pin drives high and low in turn (blinking) to indicate
TX data transfer going on whenever the host controller sends bulk out data
transfer.
Test pin. For normal operation, user should connect to ground.
Test pin. For normal operation, user should connect to ground.
Test pin. For normal operation, user should keep this pin NC.
Test pin. For normal operation, user should keep this pin NC.
Test pin. For normal operation, user should keep this pin NC.
On-chip Regulator Pins
3.3V Power supply to on-chip 3.3V-to-1.8V voltage regulator.
Ground pin of on-chip 3.3V-to-1.8V voltage regulator.
1.8V voltage output of on-chip 3.3V-to-1.8V voltage regulator.
Power and Ground Pins
13, 14, 27, 33,
41, 57, 66,
21, 51, 65
Digital I/O Power. 3.3V.
15, 16, 29, 42,
55, 56, 76
69
Analog Power for USB transceiver. 3.3V.
70
Analog Ground for USB transceiver.
74
Analog Power for USB PLL. 3.3V.
75
Analog Ground for USB PLL.
2
Analog Power for Ethernet PHY bandgap. 3.3V.
3
Analog Ground for Ethernet PHY.
6, 77
Analog Power for Ethernet PHY and 25Mhz crystal oscillator. 1.8V.
9, 80
Analog Ground for Ethernet PHY and 25Mhz crystal oscillator.
GPIO_0 / PME
B5/PD
36
SI_3
B5/PU
37
SI_2
B5/PU
38
SI_1
B5/PU
39
SI_0
B5/PU
40
USB_LED
O5
28
TEST0
TEST1
TCLK_EN
TCLK_0
TCLK_1
I5/S
I5/S
I5/PD/S
I5/PD
I5/PD
54
53
50
49
48
VCC3R3
GND3R3
V18F
P
P
P
11
12
10
VCCK
P
Digital Core Power. 1.8V.
VCC3IO
GND
P
P
Digital Ground.
VCC33A_H
GND33A_H
VCC33A_PLL
GND33A_PLL
VCC3A3
GND3A3
VCC18A
GND18A
P
P
P
P
P
P
P
P
External Media Interface: MAC Mode with MII Interface
17
Receive Clock.
RXCLK is received from PHY to provide timing reference
for the transfer of RXD [3:0] and RXDV signals on receive direction of
MII interface.
18
Receive Data Valid.
RXDV is asserted high when valid data is present on
RXD [3:0]. It is driven synchronously with respect to RXCLK by PHY.
19, 20,
22, 23
by PHY.
31
Carrier Sense. CRS is asserted high asynchronously by the PHY when
either transmit or receive medium is non-idle.
32
Collision. COL is driven high by PHY when the collision is detected.
RXCLK
I5/PD
RXDV
I5/PD
RXD [3:0]
I5/PD
Receive Data.
RXD [3:0] is driven synchronously with respect to RXCLK
CRS
I5/PD
COL
I5/PD