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參數(shù)資料
| 型號(hào)： | AX88196L |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 10/100BASE 3-in-1 Local CPU Bus Fast Ethernet Controller with Embedded SRAM |
| 中文描述： | 一個(gè)10/100Base 3合1本地CPU總線快速以太網(wǎng)控制器與嵌入式靜態(tài)存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 16/42頁(yè) |
| 文件大?。?/td> | 594K |
| 代理商： | AX88196L |
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AX88196 Local CPU BUS MAC Controller
ASIX ELECTRONICS CORPORATION
16
4.0 Registers Operation
All registers of MAC Core are 8-bit wide and mapped into pages which are selected by PS in the
Command Register.
PAGE 0 (PS1=0,PS0=0)
OFFSET
READ
00H
Command Register
( CR )
01H
Page Start Register
( PSTART )
02H
Page Stop Register
( PSTOP )
03H
Boundary Pointer
( BNRY )
04H
Transmit Status Register
( TSR )
05H
Number of Collisions Register
( NCR )
06H
Current Page Register
( CPR )
07H
Interrupt Status Register
( ISR )
08H
Current Remote DMA Address 0
( CRDA0 )
09H
Current Remote DMA Address 1
( CRDA1 )
0AH
Reserved
WRITE
Command Register
( CR )
Page Start Register
( PSTART )
Page Stop Register
( PSTOP )
Boundary Pointer
( BNRY )
Transmit Page Start Address
( TPSR )
Transmit Byte Count Register 0
( TBCR0 )
Transmit Byte Count Register 1
( TBCR1 )
Interrupt Status Register
( ISR )
Remote Start Address Register 0
( RSAR0 )
Remote Start Address Register 1
( RSAR1 )
Remote Byte Count 0
( RBCR0 )
Remote Byte Count 1
( RBCR1 )
Receive Configuration Register
( RCR )
Transmit Configuration Register ( TCR )
0BH
Reserved
0CH
Receive Status Register
( RSR )
Frame Alignment Errors
( CNTR0 )
CRC Errors
( CNTR1 )
Missed Packet Errors
( CNTR2 )
Data Port
IFGS1
IFGS2
MII/EEPROM Access
-
Inter-frame Gap (IFG)
Reserved
Standard Printer Port (SPP)
Reserved
Reset
0DH
0EH
Data Configuration Register
( DCR )
Interrupt Mask Register
( IMR )
Data Port
IFGS1
IFGS2
MII/EEPROM Access
Test Register
Inter-frame Gap (IFG)
Reserved
Standard Printer Port (SPP)
Reserved
Reserved
0FH
10H, 11H
12H
13H
14H
15H
16H
17H
18H - 1AH
1BH - 1EH
1FH
Tab - 10 Page 0 of MAC Core Registers Mapping
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