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參數(shù)資料
| 型號： | AX88170L |
| 廠商： | ASIX Electronics Corporation |
| 英文描述： | USB to Fast Ethernet/HomePNA Controller |
| 中文描述： | USB到快速以太網(wǎng)/電話線網(wǎng)絡(luò)控制器 |
| 文件頁數(shù)： | 7/39頁 |
| 文件大?。?/td> | 316K |
| 代理商： | AX88170L |
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ASIX ELECTRONICS CORPORATION
7
CONFIDENTIAL
AX88170 PRELIMINARY
2.0 Signal Description
The following terms describe the AX88170 pin-out:
All pin names with the “/” suffix are asserted low.
The following abbreviations are used in following Tables.
I
Input
O
Output
I/O
Input/Output
OD
Open Drain
PU
PD
P
Pull Up
Pull Down
Power Pin
2.1 USB Bus Interface Signals Group
SIGNAL
TYPE
D+
I/O
D-
I/O
PIN NO.
1
2
DESCRIPTION
USB Data Plus Pin
USB Data Minus Pin
Tab – 1 USB bus interface signals group
2.2 EEPROM Signals Group
SIGNAL
TYPE
EECS
EECK
EEDI
EEDO
I/PU
PIN NO.
45
46
47
48
DESCRIPTION
O
O
O
EEPROM Chip Select : EEPROM chip select signal.
EEPROM Clock : Signal connected to EEPROM clock pin.
EEPROM Data In : Signal connected to EEPROM data input pin.
EEPROM Data Out : Signal connected to EEPROM data output pin.
Tab – 2 EEPROM bus interface signals group
2.3a MII interface signals group (MAC mode)
When /S_RMII=1 and /S_MAC=0
SIGNAL
TYPE
PIN NO.
RXD[3:0]
27, 26
CRS
I/PD
15
DESCRIPTION
I/PU
29, 28
Receive Data: RXD[3:0] is driven by the PHY synchronously with respect
to RX_CLK.
Carrier Sense: Asynchronous signal CRS is asserted by the PHY when
either the transmit or receive medium is non-idle.
Receive Data Valid: RX_DV is driven by the PHY synchronously with
respect to RX_CLK. Asserted high when valid data is present on RXD
[3:0].
Receive Error: RX_ER is driven by PHY and synchronous to RX_CLK, is
asserted for one or more RX_CLK periods to indicate to the port that an
error has detected.
Receive Clock: RX_CLK is a continuous clock that provides the timing
reference for the transfer of the RX_DV,RXD[3:0] and RX_ER signals from
the PHY to the MII port of the MAC.
Collision: this signal is driven by PHY when collision is detected.
Transmit Enable: TX_EN is transition synchronously with respect to the
rising edge of TX_CLK. TX_EN indicates that the port is presenting
RX_DV
I/PD
32
RX_ER
I/PD
31
RX_CLK
I/PU
24
COL
TX_EN
I/PD
O
13
22
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AX88172A | USB 2.0 to 10/100M Fast Ethernet Controller |
| AX88172ATF | USB 2.0 to 10/100M Fast Ethernet Controller |
| AX88772A | USB 2.0 to 10/100M Fast Ethernet Controller |
| AX88772ALF | USB 2.0 to 10/100M Fast Ethernet Controller |
| AX88172L | USB to Fast Ethernet/HomePNA Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AX88172 | 制造商:ASI 制造商全稱:ASI 功能描述:USB2.0 TO ETHERNET Device setup guide |
| AX88172A | 制造商:ASIX 制造商全稱:ASIX 功能描述:USB 2.0 to 10/100M Fast Ethernet Controller |
| AX88172ATF | 制造商:ASIX 制造商全稱:ASIX 功能描述:USB 2.0 to 10/100M Fast Ethernet Controller |
| AX88172L | 制造商:ASIX 制造商全稱:ASIX 功能描述:USB to Fast Ethernet/HomePNA Controller |
| AX88178 | 制造商:ASIX 制造商全稱:ASIX 功能描述:USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller |
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