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參數(shù)資料
| 型號： | AX500-1FGG676 |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 244/262頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA AXCELERATOR 500K 676FBGA |
| 標準包裝： | 40 |
| 系列： | Axcelerator |
| 邏輯元件/單元數(shù)： | 5376 |
| RAM 位總計： | 73728 |
| 輸入/輸出數(shù)： | 336 |
| 門數(shù)： | 500000 |
| 電源電壓： | 1.425 V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-FBGA（27x27） |
Detailed Specifications
2- 68
R e v i sio n 1 8
Routed Clocks
The routed clock (CLK) is a low-skew network that can drive the clock inputs of all sequential modules in
the device (logically equivalent to the HCLK), but has the added flexibility in that it can drive the S0
(Enable), S1, PSET, and CLR input of a register (R-cells and I/O registers) as well as any of the inputs of
any C-cell in the device. This allows CLKs to be used not only as clocks, but also for other global signals
or high fanout nets. All four CLKs are available everywhere on the chip.
Timing Characteristics
Table 2-75 AX125 Routed Array Clock Networks
Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70°C
–2 Speed
–1 Speed
Std Speed
Units
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Routed Array Clock Networks
tRCKL
Input Low to High
3.08
3.50
4.12
ns
tRCKH
Input High to Low
3.13
3.56
4.19
ns
tRPWH
Minimum Pulse Width High
0.57
0.64
0.75
ns
tRPWL
Minimum Pulse Width Low
0.52
0.59
0.69
ns
tRCKSW
Maximum Skew
0.35
0.39
0.46
ns
tRP
Minimum Period
1.15
1.31
1.54
ns
tRMAX
Maximum Frequency
870
763
649
MHz
Table 2-76 AX250 Routed Array Clock Networks
Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70°C
–2 Speed
–1 Speed
Std Speed
Units
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Routed Array Clock Networks
tRCKL
Input Low to High
2.52
2.87
3.37
ns
tRCKH
Input High to Low
2.59
2.95
3.47
ns
tRPWH
Minimum Pulse Width High
0.57
0.64
0.75
ns
tRPWL
Minimum Pulse Width Low
0.52
0.59
0.69
ns
tRCKSW
Maximum Skew
0.35
0.39
0.46
ns
tRP
Minimum Period
1.15
1.31
1.54
ns
tRMAX
Maximum Frequency
870
763
649
MHz
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AX500-1FGG676I | 功能描述:IC FPGA AXCELERATOR 500K 676FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Axcelerator 產(chǎn)品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| AX500-1FGG676M | 制造商:Microsemi Corporation 功能描述:FPGA Axcelerator Family 286K Gates 5376 Cells 763MHz 0.15um Technology 1.5V 676-Pin FBGA 制造商:Microsemi Corporation 功能描述:FPGA AXCELERATOR 286K GATES 5376 CELLS 763MHZ 0.15UM 1.5V 67 - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 336 I/O 676FBGA 制造商:Microsemi Corporation 功能描述:IC FPGA AXCELERATOR 500K 676FBGA |
| AX500-1FGG896 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs |
| AX500-1FGG896B | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs |
| AX500-1FGG896I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs |
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