Axcelerator Family FPGAs
Re vi s i on 18
2-3
Table 2-4 Default CLOAD/VCCI
CLOAD (pF)
VCCI (V)
PLOAD
(mw/MHz)
P10 (mw/MHz)
PI/O (mW/MHz)*
Single-Ended without VREF
LVTTL 24 mA High Slew
35
3.3
381.2
267.5
648.7
LVTTL 16 mA High Slew
35
3.3
381.2
225.1
606.3
LVTTL 12 mA High Slew
35
3.3
381.2
165.9
547.1
LVTTL 8 mA High Slew
35
3.3
381.2
130.3
511.5
LVTTL 24 mA Low Slew
35
3.3
381.2
169.2
550.4
LVTTL 16 mA Low Slew
35
3.3
381.2
150.8
532.0
LVTTL 12 mA Low Slew
35
3.3
381.2
138.6
519.8
LVTTL 8 mA Low Slew
35
3.3
381.2
118.7
499.9
LVCMOS – 25
35
2.5
218.8
148.0
366.8
LVCMOS – 18
35
1.8
113.4
73.4
186.8
LVCMOS – 15 (JESD8-11)
35
1.5
78.8
49.5
128.3
PCI
10
3.3
108.9
218.5
327.4
PCI-X
10
3.3
108.9
162.9
271.8
Single-Ended with VREF
HSTL-I
20
1.5
–
40.9
SSTL2-I
30
2.5
–
171.2
SSTL2-II
30
2.5
–
147.8
SSTL3-I
30
3.3
–
327.2
SSTL3-II
30
3.3
–
288.4
GTLP – 25
10
2.5
–
61.5
GTLP – 33
10
3.3
–
68.5
Differential
LVPECL – 33
N/A
3.3
–
260.6
LVDS – 25
N/A
2.5
–
145.8
Note:
*PI/O = P10 + CLOAD * VCCI
2