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參數(shù)資料
| 型號(hào)： | AX125-FG256I |
| 廠商： | Microsemi SoC |
| 文件頁(yè)數(shù)： | 27/262頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA AXCELERATOR 125K 256FBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | Axcelerator |
| 邏輯元件/單元數(shù)： | 1344 |
| RAM 位總計(jì)： | 18432 |
| 輸入/輸出數(shù)： | 138 |
| 門(mén)數(shù)： | 125000 |
| 電源電壓： | 1.425 V ~ 1.575 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-FPBGA（17x17） |
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Detailed Specifications
2- 10 8
R ev isio n 1 8
TDO
TDO is normally tristated, and it is active only when the TAP controller is in the "Shift_DR" state or
"Shift_IR" state. The least significant bit of the selected register (i.e. IR or DR) is clocked out to TDO first
by the falling edge of TCK.
TAP Controller
The TAP Controller is compliant with the IEEE Standard 1149.1. It is a state machine of 16 states that
controls the Instruction Register (IR) and the Data Registers (such as BSR, IDCODE, USRCODE,
BYPASS, etc.). The TAP Controller steps into one of the states depending on the sequence of TMS at
the rising edges of TCK.
Instruction Register (IR)
The IR has five bits (IR4 to IR0). At the TRST state, IR is reset to IDCODE. Each time when IR is
selected, it goes through "select IR-Scan," "Capture-IR," "Shift-IR," all the way through "Update-IR."
When there is no test error, the first five data bits coming out of TDO during the "Shift-IR" will be "10111".
If a test error occurs, the last three bits will contain one to three zeroes corresponding to negatively
asserted signals: "TDO_ERRORB," "PROBA_ERRORB," and "PROBB_ERRORB." The error(s) will be
erased when the TAP is at the "Update-IR" or the TRST state. When in user mode start-up sequence, if
the micro-probe has not been used, the "PROBA_ERRORB" is used as a "Power-up done successfully"
flag.
Data Registers (DRs)
Data registers are distributed throughout the chip. They store testing/programming vectors. The MSB of
a data register is connected to TDI, while the LSB is connected to TDO. There are different types of data
registers. Descriptions of the main registers are as follow:
1. IDCODE:
The IDCODE is a 20-bit hard coded JTAG Silicon Signature. It is a hardwired device ID code,
which contains the Microsemi identity, part number, and version number in a specific JTAG
format.
2. USERCODE:
The USERCODE is a 33-bit programmable register. However, only 20 bits are allocated to use as
JTAG Silicon Signature. It is a supplementary identity code for the user to program information to
distinguish different programmed parts. USERCODE fuses will read out as "zeroes" when not
programmed, so only the "1" bits need to be programmed.
3. Boundary-Scan Register (BSR):
Each I/O contains three Boundary-Scan Cells. Each cell has a shift register bit, a latch, and two
MUXes. The boundary-scan cells are used for the Output-enable (E), Output (O), and Input (I)
registers. The bit order of the boundary-scan cells for each of them is E-O-I. The boundary-scan
cells are then chained serially to form the Boundary-Scan Register (BSR). The length of the BSR
is the number of I/Os in the die multiplied by three.
4. Bypass Register (BYR):
This is the "1-bit" register. It is used to shorten the TDI-TDO serial chain in board-level testing to
only one bit per device not being tested. It is also selected for all "reserved" or unused
instructions.
Probing
Internal activities of the JTAG interface can be observed via the Silicon Explorer II probes: "PRA," "PRB,"
"PRC," and "PRD."
Special Fuses
Security
Microsemi antifuse FPGAs, with FuseLock technology, offer the highest level of design security available
in a programmable logic device. Since antifuse FPGAs are live-at power-up, there is no bitstream that
can be intercepted, and no bitstream or programming data is ever downloaded to the device during
power-up, thus protecting against device cloning. In addition, special security fuses are hidden
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| AX125-FG324 | 功能描述:IC FPGA AXCELERATOR 125K 324FBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Axcelerator 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門(mén)數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
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