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參數(shù)資料
| 型號(hào)： | AV9107C-10CS08 |
| 英文描述： | CPU Frequency Generator |
| 中文描述： | CPU頻率發(fā)生器 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大小： | 504K |
| 代理商： | AV9107C-10CS08 |
4
AV9107C
PIN NUMBER
-03
14
1
2
3
4
5
6
PIN NAME
TYPE
DESCRIPTION
-05/-10
1
5
-11
14
1
2
3
4
5
FS0
FS1
FS2
FS3
AGND
GND
PD
SLOW CLOCK
Input
Input
Input
Input
-
-
Input
Input
Frequency Select 0 for CLK1 (-03 and -11 have pull-ups).
Frequency Select 1 for CLK1 (-03 and -11 have pull-ups).
Frequency Select 2 for CLK1 (-03 and -11 have pull-ups).
Frequency Select 3 for CLK1 (-03 and -11 have pull-ups).
Analog GROUND.
Digital GROUND.
POWER-DOWN. Shuts off chip when low. Internal pull-up.
SLOW CLOCK input. Forces CLK1 to 8 MHz (regardless of
FS condition). Has internal pull-up.
CRYSTAL OUTPUT or INPUT CLOCK frequency. Typically
14.318 MHz system clock. This input includes load
capacitance and feedback bias for a crystal.
CRYSTAL OUTPUT (No Connect when clock used.) This
input includes XTAL load capacitance.
OUTPUT ENABLE. Tristates REFCLK when low. Has
internal pull-up.
OUTPUT ENABLE. Tristates CLK1 when low. Has internal
pull-up.
CLOCK1 Output (see decoding tables).
Digital power supply.
REFERENCE CLOCK output. Produces a buffered version of
the input clock or crystal frequency (typically 14.318 MHz).
2
6
3
7
7
X1/ICLK
Input
4
8
8
X2
Output
9
9
OE(REFCLK)
Input
10
10
OE(CLK1)
Input
6
7
8
11
12
13
11
12
13
CLK1
VDD
REFCLK
Output
-
Output
Pin Descriptions for AV9107C-03, AV9107C-05, AV9107C-10 and AV9107C-11
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AV9107C-10CS8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU System Clock Generator |
| AV9107C11 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC |
| AV9107C-11 | 制造商:ICS 功能描述:AV9107C-11 |
| AV9107C-11CN14 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU System Clock Generator |
| AV9107C-11CS14 | 制造商:ICS 制造商全稱:ICS 功能描述:CPU Frequency Generator |
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