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參數(shù)資料
| 型號(hào)： | ATW2815S-SLV |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大?。?/td> | 113K |
| 代理商： | ATW2815S-SLV |
5
ATW2815D
TABLE II - Electrical Performance Characteristics (continued)
Test
Symbol
Conditions
-55
°
C
≤
T
C
≤
+125
°
C
V
IN
= 28VDC ±5%, C
L
= 0 UNLESS
OTHERWISE SPECIFIED
Group A
Subgroups
Device
Type
Limits
Unit
Min
Max
Output response to step
transient load changes
7/ 9/ 10/
VO
TLOAD
50% load to/from 100% load
4, 5, 6
All
-300
+300
mV pk
No load to 100% load
4, 5, 6
All
-800
-800
mV pk
100% load to no load
4, 5, 6
All
+800
+800
Recovery time, step
transient load changes
1/ 7/
TT
LOAD
50% load to/from 100% load
4, 5, 6
All
25
us
No load to 50% load
4, 5, 6
All
500
us
50% load to no load
4, 5, 6
All
7
ms
Output response to
transient step line changes
5/ 12/
VO
TLINE
Input step from 18 to 40VDC
4, 5, 6
All
+180
mV pk
Input step from 40 to 18VDC
4, 5, 6
All
-600
mV pk
Recovery time transient
step line changes 1/ 5/ 12/
TT
LINE
Input step from 18 to 40VDC
4, 5, 6
All
400
us
Input step from 40 to 18VDC
4, 5, 6
All
400
us
Turn-on overshoot
VTON
OS
I
OUT
= 0, 2000mA
4, 5, 6
All
750
mV pk
Turn-on delay 2/
TON
D
I
OUT
= 0, 2000mA
4, 5, 6
All
12
ms
Load fault recovery 12/
Tr
LF
V
IN
= 18 to 40 VDC
4, 5, 6
All
12
Weight
Flange
75
grams
Notes:
1/ Recovery time is measured from the initiation of the transient to where V
OUT
has returned to within ±1% of V
OUT
at 50% load.
2/ Turn-on delay time measurement is for either a step application of power at the input or the removal of a ground signal from the inhibit pin (pin 8) while
power is applied to the input.
3/ An overload is that condition with a load in excess of the rated load but less than that necessary to trigger the short circuit protection and is the condition
of maximum power dissipation.
4/ Above +125
°
C case, derate output power linearly to 0 at +135
°
C case.
5/ Input step transition time between 2 and 10 microseconds.
6/ Capacitive load may be any value from 0 to the maximum limit without compromising DC performance. A capacitive load in excess of the maximum
limit will not disturb loop stability but will interfere with the operation of the load fault detection circuitry, appearing as a short circuit during turn on.
7/ Load step transition time between 2 and 10 microseconds.
8/ Bandwidth guaranteed by design. Tested for 20 KHz.
9/ Load current split equally between +V
OUT
and -V
OUT.
10/ When operating with unbalanced loads, at least 25% of the load must be on the positive output to maintain regulation.
11/ Parameter guaranteed by line and load regulation tests.
12/ Parameter shall be tested as part of design characterization and after design or process changes. Thereafter parameters shall be guaranteed to the limits
specified in Table II.
13/ Up to 90% of full power is available from either output provided the total output does not exceed 30 watts.
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