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參數(shù)資料
| 型號： | ATUC128D3-Z2UR |
| 廠商： | Atmel |
| 文件頁數(shù)： | 269/755頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32BIT 128KB FLASH 64VQFN |
| 標(biāo)準(zhǔn)包裝： | 4,000 |
| 系列： | AVR®32 UC3 D |
| 核心處理器： | AVR |
| 芯體尺寸： | 32-位 |
| 速度： | 48MHz |
| 連通性： | I²C，SPI，UART/USART，USB |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，DMA，I²S，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 51 |
| 程序存儲器容量： | 128KB（128K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 16K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.65 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 64-VFQFN 裸露焊盤 |
| 包裝： | 帶卷 (TR) |
340
32133D–11/2011
UC3D
20.6 Functional Description
20.6.1
Baud Rate Generator
The baud rate generator provides the bit period clock named the Baud Rate Clock to both
receiver and transmitter. It is based on a 16-bit divider, which is specified in the Clock Divider
field in the Baud Rate Generator Register (BRGR.CD). A non-zero value enables the generator,
and if CD is one, the divider is bypassed and inactive. The Clock Selection field in the Mode
Register (MR.USCLKS) selects clock source between:
CLK_USART (internal clock)
CLK_USART/DIV (a divided CLK_USART, refer to Module Configuration section)
CLK (external clock, available on the CLK pin)
If the external CLK clock is selected, the duration of the low and high levels of the signal pro-
vided on the CLK pin must be at least 4.5 times longer than those provided by CLK_USART.
Figure 20-2. Baud Rate Generator
20.6.1.1
Baud Rate in Asynchronous Mode
If the USART is configured to operate in an asynchronous mode, the selected clock is divided by
the CD value before it is provided to the receiver as a sampling clock. Depending on the Over-
sampling Mode bit (MR.OVER) value, the clock is then divided by either 8 (OVER=1), or 16
(OVER=0). The baud rate is calculated with the following formula:
This gives a maximum baud rate of CLK_USART divided by 8, assuming that CLK_USART is
the fastest clock possible, and that OVER is one.
20.6.1.2
Baud Rate Calculation Example
Table 20-3 shows calculations based on the CD field to obtain 38400 baud from different source
clock frequencies. This table also shows the actual resulting baud rate and error.
16-bit Counter
CD
USCLKS
CD
CLK_USART
CLK_USART/DIV
Reserved
CLK
SYNC
USCLKS= 3
FIDI
OVER
Sampling
Divider
BaudRate
Clock
Sampling
Clock
1
0
CLK
0
1
2
3
>1
1
0
BaudRate
SelectedClock
82 OVER
–
()CD
()
------------------------------------------------
=
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ATUC128D3-Z2UT | 功能描述:32位微控制器 - MCU UC3D3 128KB FL 85C RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
| ATUC128D4-AUR | 功能描述:32位微控制器 - MCU UC3D4 128KB FL 85C RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
| ATUC128D4-AUT | 功能描述:32位微控制器 - MCU UC3D4 128KB FL 85C RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
| ATUC128D4-Z1UR | 功能描述:32位微控制器 - MCU UC3D4 128KB FL 85C RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
| ATUC128D4-Z1UT | 功能描述:32位微控制器 - MCU UC3D4 128KB FL 85C RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
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