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參數(shù)資料
| 型號： | ATTINY45-20MI |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, QCC20 |
| 封裝： | 4 X 4 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, MO-220WGGD5, MLF-20 |
| 文件頁數(shù)： | 23/91頁 |
| 文件大?。?/td> | 19688K |
| 代理商： | ATTINY45-20MI |
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34
7707F–AVR–11/10
AT90USB82/162
6.6
External Clock
The device can utilize a external clock source as shown in Figure 6-5. To run the device on an
external clock, the CKSEL Fuses must be programmed as shown in Table 6-1.
Figure 6-5.
External Clock Drive Configuration
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in
When applying an external clock, it is required to avoid sudden changes in the applied clock fre-
quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from
one clock cycle to the next can lead to unpredictable behavior. If changes of more than 2% is
required, ensure that the MCU is kept in Reset during the changes.
Note that the System Clock Prescaler can be used to implement run-time changes of the internal
clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page
34 for details.
6.7
Clock Output Buffer
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT
Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir-
cuits on the system. The clock also will be output during reset, and the normal operation of I/O
pin will be overridden when the fuse is programmed. Any clock source, including the internal RC
Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is
used, it is the divided system clock that is output.
6.8
System Clock Prescaler
The AT90USB82/162 has a system clock prescaler, and the system clock can be divided by set-
ting the “Clock Prescale Register – CLKPR” on page 35. This feature can be used to decrease
Table 6-8.
Start-up Times for the External Clock Selection
Power Conditions
Start-up Time from Power-
down and Power-save
Additional Delay from
Reset (VCC = 5.0V)
SUT1..0
BOD enabled
6 CK
14CK
00
Fast rising power
6 CK
14CK + 4.1 ms
01
Slowly rising power
6 CK
14CK + 65 ms
10
Reserved
11
NC
EXTERNAL
CLOCK
SIGNAL
XTAL2
XTAL1
GND
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