參數(shù)資料
型號: ATTINY44-20MUR
廠商: Atmel
文件頁數(shù): 98/238頁
文件大?。?/td> 0K
描述: MCU AVR 4KB FLASH 20MHZ 20QFN
產(chǎn)品培訓模塊: tinyAVR Introduction
標準包裝: 6,000
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 20MHz
連通性: USI
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 12
程序存儲器容量: 4KB(2K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-WFQFN 裸露焊盤
包裝: 帶卷 (TR)
其它名稱: ATTINY44-20MUR-ND
ATTINY44-20MURTR
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2000 Microchip Technology Inc.
DS39026C-page 185
PIC18CXX2
18.3
Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared, but
keeps running, the PD bit (RCON<3>) is cleared, the
TO (RCON<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external cir-
cuitry is drawing current from the I/O pin, power-down
the A/D and disable external clocks. Pull all I/O pins
that are hi-impedance inputs, high or low externally, to
avoid switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (VIHMC).
18.3.1
WAKE-UP FROM SLEEP
The device can wake up from SLEEP through one of
the following events:
1.
External RESET input on MCLR pin.
2.
Watchdog
Timer
Wake-up
(if
WDT
was
enabled).
3.
Interrupt from INT pin, RB port change, or a
Peripheral Interrupt.
The following peripheral interrupts can wake the device
from SLEEP:
1.
PSP read or write.
2.
TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
3.
TMR3 interrupt. Timer3 must be operating as an
asynchronous counter.
4.
CCP capture mode interrupt.
5.
Special event trigger (Timer1 in Asynchronous
mode using an external clock).
6.
MSSP (START/STOP) bit detect interrupt.
7.
MSSP transmit or receive in Slave mode
(SPI/I2C).
8.
USART RX or TX (Synchronous Slave mode).
9.
A/D conversion (when A/D clock source is RC).
Other peripherals cannot generate interrupts, since
during SLEEP, no on-chip clocks are present.
External MCLR Reset will cause a device RESET. All
other events are considered a continuation of program
execution and will cause a “wake-up”. The TO and PD
bits in the RCON register can be used to determine the
cause of the device RESET. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared, if a WDT time-out occurred (and caused
wake-up).
When the SLEEP instruction is being executed, the next
instruction (PC + 2) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.
18.3.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
If an interrupt condition (interrupt flag bit and inter-
rupt enable bits are set) occurs before the execu-
tion of a SLEEP instruction, the SLEEP instruction
will complete as a NOP. Therefore, the WDT and
WDT postscaler will not be cleared, the TO bit will
not be set and PD bits will not be cleared.
If the interrupt condition occurs during or after
the execution of a SLEEP instruction, the device
will immediately wake up from SLEEP. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP
instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruc-
tion should be executed before a SLEEP instruction.
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