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    參數(shù)資料
    型號: ATTINY15L-1PC
    廠商: Atmel
    文件頁數(shù): 31/85頁
    文件大?。?/td> 0K
    描述: IC AVR MCU 1K FLASH 2.7V 8DIP
    標(biāo)準(zhǔn)包裝: 50
    系列: AVR® ATtiny
    核心處理器: AVR
    芯體尺寸: 8-位
    速度: 1.6MHz
    外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
    輸入/輸出數(shù): 6
    程序存儲器容量: 1KB(512 x 16)
    程序存儲器類型: 閃存
    EEPROM 大?。?/td> 64 x 8
    電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
    數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
    振蕩器型: 內(nèi)部
    工作溫度: 0°C ~ 70°C
    封裝/外殼: 8-DIP(0.300",7.62mm)
    包裝: 管件
    37
    ATtiny15L
    1187H–AVR–09/07
    The EEPROM Control Register
    – EECR
    Bit 7..4 – RES: Reserved Bits
    These bits are reserved bits in the ATtiny15L and will always read as zero.
    Bit 3 – EERIE: EEPROM Ready Interrupt Enable
    When the I-bits in SREG and EERIE are set (one), the EEPROM Ready Interrupt is
    enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready Interrupt
    generates a constant interrupt when EEWE is cleared (zero).
    Bit 2 – EEMWE: EEPROM Master Write Enable
    The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be
    written. When EEMWE is set (one), setting EEWE will write data to the EEPROM at the
    selected address. If EEMWE is zero, setting EEWE will have no effect. When EEMWE
    has been set (one) by software, hardware clears the bit to zero after four clock cycles.
    See the description of the EEWE bit for an EEPROM write procedure.
    Bit 1 – EEWE: EEPROM Write Enable
    The EEPROM Write Enable Signal – EEWE – is the write strobe to the EEPROM. When
    address and data are correctly set up, the EEWE bit must be set to write the value in to
    the EEPROM. The EEMWE bit must be set when the logical “1” is written to EEWE, oth-
    erwise no EEPROM write takes place. The following procedure should be followed
    when writing the EEPROM (the order of steps 2 and 3 is not essential):
    1.
    Wait until EEWE becomes zero.
    2.
    Write new EEPROM address to EEAR (optional).
    3.
    Write new EEPROM data to EEDR (optional).
    4.
    Write a logical “1” to the EEMWE bit in EECR.
    5.
    Within four clock cycles after setting EEMWE, write a logical “1” to EEWE.
    Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the
    EEPROM Master Write Enable will time-out. If an interrupt routine accessing the
    EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be
    modified, causing the interrupted EEPROM access to fail. It is recommended to have
    the Global Interrupt Flag cleared during the four last steps to avoid these problems.
    When the write access time (typically 5.1 ms if the internal RC Oscillator is calibrated to
    1.6 MHz) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software
    can poll this bit and wait for a zero before writing the next byte. When EEWE has been
    set, the CPU is halted for two cycles before the next instruction is executed.
    Bit 0 – EERE: EEPROM Read Enable
    The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the
    correct address is set up in the EEAR Register, the EERE bit must be set. When the
    EERE bit is cleared (zero) by hardware, requested data is found in the EEDR Register.
    The EEPROM read access takes one instruction and there is no need to poll the EERE
    bit. When EERE has been set, the CPU is halted for four cycles before the next instruc-
    tion is executed.
    Bit
    7
    65
    43
    2
    1
    0
    $1C
    EERIE
    EEMWE
    EEWE
    EERE
    EECR
    Read/Write
    R
    R/W
    Initial value
    0
    X
    0
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