參數(shù)資料
型號: ATSAM3A8CA-CU
廠商: Atmel
文件頁數(shù): 22/71頁
文件大?。?/td> 0K
描述: IC MCU 2X256KB CORTEX-M3 100-BGA
標(biāo)準(zhǔn)包裝: 260
系列: SAM3A
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 84MHz
連通性: CAN,I²C,IrDA,LIN,MMC,SPI,SSC,UART/USART,USB
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 63
程序存儲(chǔ)器容量: 512KB(512K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 96K x 8
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TFBGA
包裝: 托盤
31
11057BS–ATARM–13-Jul-12
SAM3X/A
31
11057BS–ATARM–13-Jul-12
SAM3X/A
6.4
NRST Pin
The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low
to provide a reset signal to the external components, or asserted low externally to reset the
microcontroller. It will reset the Core and the peripherals except the Backup region (RTC, RTT
and Supply Controller). There is no constraint on the length of the reset pulse, and the reset con-
troller can guarantee a minimum pulse length.
The NRST pin integrates a permanent pull-up resistor to VDDIO of about 100 k
Ω.
6.5
NRSTB Pin
The NRSTB pin is input only and enables asynchronous reset of the SAM3X/A series when
asserted low. The NRSTB pin integrates a permanent pull-up resistor of about 15 k
Ω. This allows
connection of a simple push button on the NRSTB pin as a system-user reset. In all modes, this
pin will reset the chip including the Backup region (RTC, RTT and Supply Controller). It reacts as
the Power-on reset. It can be used as an external system reset source. In harsh environments, it
is recommended to add an external capacitor (10 nF) between NRSTB and VDDBU. (For filter-
ing values, refer to “I/O characteristics” in the “Electrical Characteristics” section of the product
datasheet)
It embeds an anti-glitch filter.
6.6
ERASE Pin
The ERASE pin is used to reinitialize the Flash content (and some of its NVM bits) to an erased
state (all bits read as logic level 1). It integrates a pull-down resistor of about 100 k
Ω to GND, so
that it can be left unconnected for normal operations.
This pin is debounced by SCLK to improve the glitch tolerance. When the ERASE pin is tied high
during less than 100 ms, it is not taken into account. The pin must be tied high during more than
220 ms to perform a Flash erase operation.
The ERASE pin is a system I/O pin and can be used as a standard I/O. At startup, the ERASE
pin is not configured as a PIO pin. If the ERASE pin is used as a standard I/O, the startup level
of this pin must be low to prevent unwanted erasing. Please refer to Section 11.2 “Peripheral
Signal Multiplexing on I/O Lines”. Also, if the ERASE pin is used as a standard I/O output,
asserting the pin to low does not erase the Flash.
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