129
7799D–AVR–11/10
ATmega8U2/16U2/32U2
Figure 16-13.
Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
16.11 Register Description
16.11.1
TCCR1A – Timer/Counter1 Control Register A
Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A
Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B
Bit 3:2 – COMnC1:0: Compare Output Mode for Channel C
The COMnA[1:0], COMnB[1:0], and COMnC[1:0] control the output compare pins (OCnA,
OCnB, and OCnC respectively) behavior. If one or both of the COMnA[1:0] bits are written to
one, the OCnA output overrides the normal port functionality of the I/O pin it is connected to. If
one or both of the COMnB[1:0] bits are written to one, the OCnB output overrides the normal
port functionality of the I/O pin it is connected to. If one or both of the COMnC[1:0] bits are writ-
ten to one, the OCnC output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OCnA, OCnB
or OCnC pin must be set in order to enable the output driver.
When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx[1:0] bits is
dependent of the WGMn[3:0] bits setting.
Table 16-1 shows the COMnx[1:0] bit functionality
when the WGMn[3:0] bits are set to a normal or a CTC mode (non-PWM).
TOVn(FPWM)
and ICF n(if used
as TOP)
OCRnx
(Update at TOP)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOP - 1
TOP
TOP - 1
TOP - 2
Old OCRnx Value
New OCRnx Value
TOP - 1
TOP
BOTTOM
BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O/8)
Bit
76543
2
1
0
COM1A1
COM1A0
COM1B1
COM1B0
COM1C1
COM1C0
WGM11
WGM10
TCCR1A
Read/Write
R/W
Initial Value
00000
0