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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� ATMEGA325P-20MUR
寤犲晢锛� Atmel
鏂囦欢闋佹暩(sh霉)锛� 103/364闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� MCU AVR 32K FLASH 20MHZ 64QFN
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� megaAVR Introduction
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 4,000
绯诲垪锛� AVR® ATmega
鏍稿績铏曠悊鍣細 AVR
鑺珨灏哄锛� 8-浣�
閫熷害锛� 20MHz
閫i€氭€э細 SPI锛孶ART/USART锛孶SI
澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯(c猫)/寰�(f霉)浣�锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 54
绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 32KB锛�16K x 16锛�
绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 闁冨瓨
EEPROM 澶�?銆�?/td> 1K x 8
RAM 瀹归噺锛� 2K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 2.7 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 8x10b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 64-VFQFN 瑁搁湶鐒婄洡
鍖呰锛� 甯跺嵎 (TR)
鍏跺畠鍚嶇ū锛� ATMEGA325P-20MUR-ND
ATMEGA325P-20MURTR
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191
8023F鈥揂VR鈥�07/09
ATmega325P/3250P
19. USI 鈥� Universal Serial Interface
19.1
Features
Two-wire Synchronous Data Transfer (Master or Slave)
Three-wire Synchronous Data Transfer (Master or Slave)
Data Received Interrupt
Wake up from Idle Mode
In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode
Two-wire Start Condition Detector with Interrupt Capability
19.2
Overview
The Universal Serial Interface, USI, provides the basic hardware resources needed for serial
communication. Combined with a minimum of control software, the USI allows significantly
higher transfer rates and uses less code space than solutions based on software only. Interrupts
are included to minimize the processor load.
A simplified block diagram of the USI is shown on Figure 19-1. For the actual placement of I/O
accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific
I/O Register and bit locations are listed in the 鈥漅egister Descriptions鈥� on page 199.
Figure 19-1. Universal Serial Interface, Block Diagram
The 8-bit Shift Register is directly accessible via the data bus and contains the incoming and
outgoing data. The register has no buffering so the data must be read as quickly as possible to
ensure that no data is lost. The most significant bit is connected to one of two output pins
depending of the wire mode configuration. A transparent latch is inserted between the Serial
Register Output and output pin, which delays the change of data output to the opposite clock
edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin
independent of the configuration.
DATA
BUS
USIPF
USITC
USICLK
USICS0
USICS1
USIOIF
USIOIE
USIDC
USISIF
USIWM0
USIWM1
USISIE
Bit7
Two-wire Clock
Control Unit
DO
(Output only)
DI/SDA
(Input/Open Drain)
USCK/SCL
(Input/Open Drain)
4-bit Counter
USIDR
USISR
DQ
LE
USICR
CLOCK
HOLD
TIM0 COMP
Bit0
[1]
3
0
1
2
3
0
1
2
0
1
2
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
SC16C750BIB64,157 IC UART 64BYTE 64LQFP
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VI-2N2-IY CONVERTER MOD DC/DC 15V 50W
VE-BTN-IX-F4 CONVERTER MOD DC/DC 18.5V 75W
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ATMEGA325PA 鍒堕€犲晢:ATMEL 鍒堕€犲晢鍏ㄧū:ATMEL Corporation 鍔熻兘鎻忚堪:8-bit Microcontroller with 16/32/64K Bytes In-System Programmable Flash
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