I
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� ATMEGA324PA-MCHR
寤犲晢锛� Atmel
鏂囦欢闋佹暩(sh霉)锛� 26/54闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� MCU AVR 32KB FLASH 20 MHZ 44QFN
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� megaAVR Introduction
妯欐簴鍖呰锛� 6,000
绯诲垪锛� AVR® ATmega
鏍稿績铏曠悊鍣細 AVR
鑺珨灏哄锛� 8-浣�
閫熷害锛� 20MHz
閫ｉ€氭€э細 I²C锛孲PI锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯/寰�(f霉)浣�锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 32
绋嬪簭瀛樺劜鍣ㄥ閲忥細 32KB锛�16K x 16锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
EEPROM 澶у皬锛� 1K x 8
RAM 瀹归噺锛� 2K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 1.8 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 8x10b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 44-VQFN 瑁搁湶鐒婄洡
鍖呰锛� 甯跺嵎 (TR)
鍏跺畠鍚嶇ū锛� ATMEGA324PA-MCHR-ND
PIC16(L)F1526/27
DS41458B-page 328
Preliminary
2011 Microchip Technology Inc.
TABLE 25-12: SPI MODE REQUIREMENTS
FIGURE 25-19:
I2C BUS START/STOP BITS TIMING
Param
No.
Symbol
Characteristic
Min.
Typ
Max. Units Conditions
SP70* TSSL2SCH,
TSSL2SCL
SSx
to SCKx or SCKx input
TCY
鈥斺€�
ns
SP71* TSCH
SCKx input high time (Slave mode)
TCY + 20
鈥�
ns
SP72* TSCL
SCKx input low time (Slave mode)
TCY + 20
鈥�
ns
SP73* TDIV2SCH,
TDIV2SCL
Setup time of SDIx data input to SCKx edge
100
鈥�
ns
SP74* TSCH2DIL,
TSCL2DIL
Hold time of SDIx data input to SCKx edge
100
鈥�
ns
SP75* TDOR
SDO data output rise time
3.0-5.5V
鈥�
10
25
ns
1.8-5.5V
鈥�
25
50
ns
SP76* TDOF
SDOx data output fall time
鈥�
10
25
ns
SP77* TSSH2DOZ SSx
to SDOx output high-impedance
10
鈥�
50
ns
SP78* TSCR
SCKx output rise time
(Master mode)
3.0-5.5V
鈥�
10
25
ns
1.8-5.5V
鈥�
25
50
ns
SP79* TSCF
SCKx output fall time (Master mode)
鈥�
10
25
ns
SP80* TSCH2DOV,
TSCL2DOV
SDOx data output valid after
SCKx edge
3.0-5.5V
鈥�
50
ns
1.8-5.5V
鈥�
145
ns
SP81* TDOV2SCH,
TDOV2SCL
SDOx data output setup to SCKx edge
Tcy
鈥�
ns
SP82* TSSL2DOV
SDOx data output valid after SS
edge
鈥�
50
ns
SP83* TSCH2SSH,
TSCL2SSH
SSx
after SCKx edge
1.5TCY + 40
鈥�
ns
* These parameters are characterized but not tested.
Data in 鈥淭yp鈥� column is at 3.0V, 25掳C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note
: Refer to
Figure 25-4 for load conditions.
SP91
SP92
SP93
SCLx
SDAx
Start
Condition
Stop
Condition
SP90
鐩搁棞(gu膩n)PDF璩囨枡
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
ATMEGA324PA-MN 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU AVR 32KB FLSH 1KB EE 2KB SRAM-20MHz 105C RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT
ATMEGA324PA-MNR 鍔熻兘鎻忚堪:20 MHZ, QFP, 105C 鍒堕€犲晢:microchip technology 绯诲垪:AVR? ATmega 鍖呰:鍓垏甯讹紙CT锛� 闆朵欢鐙€鎱�(t脿i):鍦ㄥ敭 鏍稿績铏曠悊鍣�:AVR 鏍稿績灏哄:8-浣� 閫熷害:20MHz 閫ｆ帴鎬�:I2C锛孲PI锛孶ART/USART 澶栬ō(sh猫):娆犲妾㈡脯/寰�(f霉)浣�锛孭OR锛孭WM锛學DT I/O 鏁�(sh霉):32 绋嬪簭瀛樺劜瀹归噺:32KB锛�16K x 16锛� 绋嬪簭瀛樺劜鍣ㄩ鍨�:闁冨瓨 EEPROM 瀹归噺:1K x 8 RAM 瀹归噺:2K x 8 闆诲 - 闆绘簮锛圴cc/Vdd锛�:1.8 V ~ 5.5 V 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒:A/D 8x10b 鎸暕鍣ㄩ鍨�:鍏�(n猫i)閮� 宸ヤ綔婧害:-40掳C ~ 105掳C锛圱A锛� 灏佽/澶栨:44-VFQFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗗櫒浠跺皝瑁�:44-VQFN锛�7x7锛� 妯欐簴鍖呰:1
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ATMEGA324PA-PN 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU AVR 32KB FLSH 1KB EE 2KB SRAM-20MHz 105C RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT
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