參數(shù)資料
型號(hào): ATMEGA16A-MUR
廠商: Atmel
文件頁數(shù): 64/88頁
文件大?。?/td> 0K
描述: MCU AVR 16KB FLASH 16MHZ 44QFN
產(chǎn)品培訓(xùn)模塊: megaAVR Introduction
標(biāo)準(zhǔn)包裝: 4,000
系列: AVR® ATmega
核心處理器: AVR
芯體尺寸: 8-位
速度: 16MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 16KB(8K x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 512 x 8
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-VFQFN 裸露焊盤
包裝: 帶卷 (TR)
2000 Microchip Technology Inc.
Preliminary
DS40197B-page 27
PIC16HV540
6.1
Using Timer0 with an External Clock
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock require-
ment is due to internal phase clock (TOSC) synchroniza-
tion. Also, there is a delay in the actual incrementing of
Timer0 after synchronization.
6.1.1
EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks (Figure 6-5).
Therefore, it is necessary for T0CKI to be high for at
least 2TOSC (and a small RC delay of 20 ns) and low for
at least 2TOSC (and a small RC delay of 20 ns). Refer
to the electrical specification of the desired device.
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter-type pres-
caler so that the prescaler output is symmetrical. For
the external clock to meet the sampling requirement,
the ripple counter must be taken into account. There-
fore, it is necessary for T0CKI to have a period of at
least 4TOSC (and a small RC delay of 40 ns) divided by
the prescaler value. The only requirement on T0CKI
high and low time is that they do not violate the mini-
mum pulse width requirement of 10 ns. Refer to param-
eters 40, 41 and 42 in the electrical specification of the
desired device.
6.1.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0 mod-
ule is actually incremented. Figure 6-5 shows the delay
from the external clock edge to the timer incrementing.
FIGURE 6-5:
TIMER0 TIMING WITH EXTERNAL CLOCK
Increment Timer0 (Q4)
External Clock Input or
Q1
Q2
Q3 Q4
Q1
Q2
Q3 Q4
Q1
Q2
Q3 Q4
Q1
Q2
Q3 Q4
Timer0
T0
T0 + 1
T0 + 2
Small pulse
misses sampling
External Clock/Prescaler
Output After Sampling
(3)
Note 1:
2:
3:
Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on Timer0 input =
± 4Tosc max.
External clock if no prescaler selected, Prescaler output otherwise.
The arrows indicate the points in time where sampling occurs.
Prescaler Output (2)
(1)
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