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21
8151H–AVR–02/11
ATmega128A
Figure 7-3.
On-chip Data SRAM Access Cycles
7.3
EEPROM Data Memory
The AtmelAVRATmega128A contains 4Kbytes of data EEPROM memory. It is organized as a
separate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the
CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register.
in SPI, JTAG, or Parallel Programming mode
7.3.1
EEPROM Read/Write Access
The EEPROM access registers are accessible in the I/O space.
The write access time for the EEPROM is given in
Table 7-2. A self-timing function, however,
lets the user software detect when the next byte can be written. If the user code contains instruc-
tions that write the EEPROM, some precautions must be taken. In heavily filtered power
supplies, V
CC is likely to rise or fall slowly on Power-up/down. This causes the device for some
period of time to run at a voltage lower than specified as minimum for the clock frequency used.
situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
7.3.2
EEPROM Write During Power-down Sleep Mode
When entering Power-down sleep mode while an EEPROM write operation is active, the
EEPROM write operation will continue, and will complete before the write access time has
passed. However, when the write operation is completed, the Oscillator continues running, and
as a consequence, the device does not enter Power-down entirely. It is therefore recommended
to verify that the EEPROM write operation is completed before entering Power-down.
7.3.3
Preventing EEPROM Corruption
During periods of low V
CC, the EEPROM data can be corrupted because the supply voltage is
too low for the CPU and the EEPROM to operate properly. These issues are the same as for
board level systems using EEPROM, and the same design solutions should be applied.
clk
WR
RD
Data
Address
Address valid
T1
T2
T3
Compute Address
Read
Write
CPU
Memory access instruction
Next instruction