參數(shù)資料
型號(hào)： ATMEGA1284-AUR
廠商： Atmel
文件頁數(shù)： 125/160頁
文件大小： 0K
描述： IC MCU AVR 128K FLASH 44TQFP
產(chǎn)品培訓(xùn)模塊： megaAVR Introduction
標(biāo)準(zhǔn)包裝： 1
系列： AVR® ATmega
核心處理器： AVR
芯體尺寸： 8-位
速度： 20MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 128KB（64K x 16）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 16K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 剪切帶 (CT)
67
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
13. External Interrupts
13.1
Overview
The External Interrupts are triggered by the INT2:0 pin or any of the PCINT31:0 pins. Observe
that, if enabled, the interrupts will trigger even if the INT2:0 or PCINT31:0 pins are configured as
outputs. This feature provides a way of generating a software interrupt.
The Pin change interrupt PCI3 will trigger if any enabled PCINT31:24 pin toggle, Pin change
interrupt PCI2 will trigger if any enabled PCINT23:16 pin toggles, Pin change interrupt PCI1 if
any enabled PCINT15:8 toggles and Pin change interrupts PCI0 will trigger if any enabled
PCINT7:0 pin toggles. PCMSK3, PCMSK2, PCMSK1 and PCMSK0 Registers control which pins
contribute to the pin change interrupts. Pin change interrupts on PCINT31:0 are detected asyn-
chronously. This implies that these interrupts can be used for waking the part also from sleep
modes other than Idle mode.
In order for a pin change interrupt (PCINT) to be generated, the device must have an active I/O
clock. As shown in Table 10-1 on page 42, the I/O clock domain is active in Idle Mode, but not in
deeper sleep modes. In sleep modes deeper than Idle Mode, a toggled pin must remain in its
toggled state until the device has fully woken up. See Section 9. ”System clock and clock
options” on page 30 for wake up times. If the pin toggles back to its initial state during wake up,
the device will still complete the procedure, but will not generate an interrupt once awake.
The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up
as indicated in the specification for the External Interrupt Control Registers – EICRA (INT2:0).
When the external interrupt is enabled and is configured as level triggered, the interrupt will trig-
ger as long as the pin is held low. Low level interrupts and the edge interrupt on INT2:0 are
detected asynchronously. This implies that these interrupts can be used for waking the part also
from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle
mode.
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If
the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-
rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described
13.2
Register description
13.2.1
EICRA – External Interrupt Control Register A
The External Interrupt Control Register A contains control bits for interrupt sense control.
Bits 7:6 – Reserved
These bits are reserved in the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P,
and will always read as zero.
Bit
76543210
–
ISC21
ISC20
ISC11
ISC10
ISC01
ISC00
EICRA
Read/Write
R
R/W
Initial Value
00000000
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