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參數(shù)資料
型號(hào): ATMEGA128-16AUR
廠商: Atmel
文件頁數(shù): 15/24頁
文件大小: 0K
描述: MCU AVR 128KB FLASH 16MHZ 64TQFP
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
megaAVR Introduction
標(biāo)準(zhǔn)包裝: 1,000
系列: AVR® ATmega
核心處理器: AVR
芯體尺寸: 8-位
速度: 16MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 53
程序存儲(chǔ)器容量: 128KB(64K x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 帶卷 (TR)
配用: ATSTK600-RC09-ND - STK600 ROUTING CARD AVR
ATSTK600-ND - DEV KIT FOR AVR/AVR32
ATSTK501-ND - ADAPTER KIT FOR 64PIN AVR MCU
ATSTK500-ND - PROGRAMMER AVR STARTER KIT
22
2467XS–AVR–06/11
ATmega128
6.
Improved description on how to do a polarity check of the ADC differential results in
“ADC Conversion Result” on page 241.
7.
Corrected JTAG version numbers in “JTAG Version Numbers” on page 256.
8.
Improved description of addressing during SPM (usage of RAMPZ) on “Addressing
the Flash During Self-Programming” on page 278, “Performing Page Erase by SPM”
on page 280, and “Performing a Page Write” on page 280.
9.
Added not regarding OCDEN Fuse below Table 118 on page 288.
10. Updated Programming Figures:
Figure 135 on page 290 and Figure 144 on page 301 are updated to also reflect that AVCC
must be connected during Programming mode. Figure 139 on page 297 added to illustrate
how to program the fuses.
11. Added a note regarding usage of the PROG_PAGELOAD and PROG_PAGEREAD
instructions on page 307.
12. Added Calibrated RC Oscillator characterization curves in section “Typical Charac-
teristics” on page 333.
13. Updated “Two-wire Serial Interface” section.
More details regarding use of the TWI Power-down operation and using the TWI as master
with low TWBRR values are added into the data sheet. Added the note at the end of the “Bit
Rate Generator Unit” on page 203. Added the description at the end of “Address Match Unit”
on page 204.
14. Added a note regarding usage of Timer/Counter0 combined with the clock. See
“XTAL Divide Control Register – XDIV” on page 36.
Rev. 2467C-02/02
1.
Corrected Description of Alternate Functions of Port G
Corrected description of TOSC1 and TOSC2 in “Alternate Functions of Port G” on page 84.
2.
Added JTAG Version Numbers for rev. F and rev. G
Updated Table 100 on page 256.
3
Added Some Preliminary Test Limits and Characterization Data
Removed some of the TBD's in the following tables and pages:
Table 19 on page 50, Table 20 on page 54, “DC Characteristics” on page 318, Table 131 on
page 320, Table 134 on page 323, and Table 136 on page 328.
4.
5.
Added some Characterization Data in Section “Typical Characteristics” on page 333..
6.
Removed Alternative Algortihm for Leaving JTAG Programming Mode.
See “Leaving Programming Mode” on page 315.
7.
Added Description on How to Access the Extended Fuse Byte Through JTAG Pro-
gramming Mode.
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