參數(shù)資料
型號(hào): ATF1508ASL-25JU84
廠商: Atmel
文件頁(yè)數(shù): 29/31頁(yè)
文件大?。?/td> 0K
描述: IC CPLD 25NS LOW PWR 84PLCC
標(biāo)準(zhǔn)包裝: 15
系列: ATF15xx
可編程類(lèi)型: 系統(tǒng)內(nèi)可編程(最少 10,000 次編程/擦除循環(huán))
最大延遲時(shí)間 tpd(1): 25.0ns
電壓電源 - 內(nèi)部: 4.5 V ~ 5.5 V
宏單元數(shù): 128
輸入/輸出數(shù): 64
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 84-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 84-PLCC(29.31x29.31)
包裝: 管件
配用: ATF15XX-DK3-ND - KIT DEV FOR ATF15XX CPLD'S
7
ATF1508AS(L)
0784P–PLD–7/05
Speed/Power
Management
The ATF1508AS has several built-in speed and power management features. The
ATF1508AS contains circuitry that automatically puts the device into a low-power stand-by
mode when no logic transitions are occurring. This not only reduces power consumption dur-
ing inactive periods, but also provides proportional power-savings for most applications
running at system speeds below 5 MHz.
To further reduce power, each ATF1508AS macrocell has a Reduced-power bit feature. This
feature allows individual macrocells to be configured for maximum power savings. This feature
may be selected as a design option.
I/O Diagram
All ATF1508 also have an optional power-down mode. In this mode, current drops to below 10
mA. When the power-down option is selected, either PD1 or PD2 pins (or both) can be used to
power down the part. The power-down option is selected in the design source file. When
enabled, the device goes into power-down when either PD1 or PD2 is high. In the power-down
mode, all internal logic signals are latched and held, as are any enabled outputs.
All pin transitions are ignored until the PD pin is brought low. When the power-down feature is
enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin’s
macrocell may still be used to generate buried foldback and cascade logic signals.
All power-down AC characteristic parameters are computed from external input or I/O pins,
with Reduced-power Bit turned on. For macrocells in reduced-power mode (Reduced-power
bit turned on), the reduced-power adder, tRPA, must be added to the AC parameters, which
include the data paths t
LAD, tLAC, tIC, tACL, tACH and tSEXP.
Each output also has individual slew rate control. This may be used to reduce system noise by
slowing down outputs that do not need to operate at maximum speed. Outputs default to slow
switching, and may be specified as fast switching in the design file.
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ATF1508ASL-25QC100 功能描述:IC CPLD 25NS LOW PWR 100PQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - CPLD(復(fù)雜可編程邏輯器件) 系列:ATF15xx 標(biāo)準(zhǔn)包裝:40 系列:ispMACH® 4000C 可編程類(lèi)型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):5.0ns 電壓電源 - 內(nèi)部:1.65 V ~ 1.95 V 邏輯元件/邏輯塊數(shù)目:32 宏單元數(shù):512 門(mén)數(shù):- 輸入/輸出數(shù):128 工作溫度:-40°C ~ 105°C 安裝類(lèi)型:表面貼裝 封裝/外殼:176-LQFP 供應(yīng)商設(shè)備封裝:176-TQFP(24x24) 包裝:托盤(pán)
ATF1508ASL-25QC160 功能描述:IC CPLD 25NS LOW PWR 160PQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - CPLD(復(fù)雜可編程邏輯器件) 系列:ATF15xx 標(biāo)準(zhǔn)包裝:40 系列:ispMACH® 4000C 可編程類(lèi)型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):5.0ns 電壓電源 - 內(nèi)部:1.65 V ~ 1.95 V 邏輯元件/邏輯塊數(shù)目:32 宏單元數(shù):512 門(mén)數(shù):- 輸入/輸出數(shù):128 工作溫度:-40°C ~ 105°C 安裝類(lèi)型:表面貼裝 封裝/外殼:176-LQFP 供應(yīng)商設(shè)備封裝:176-TQFP(24x24) 包裝:托盤(pán)
ATF1508ASL-25QI100 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD 128 MACROCELL 5V 25NS IND TEMP RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
ATF1508ASL-25QI160 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD 128 MACROCELL 5V 25NS IND TEMP RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
ATF1508ASV 制造商:ATMEL 制造商全稱(chēng):ATMEL Corporation 功能描述:Highperformance EE PLD