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參數(shù)資料
| 型號： | ATF1508AS-10QI100 |
| 文件頁數(shù)： | 1/69頁 |
| 文件大?。?/td> | 601K |
| 代理商： | ATF1508AS-10QI100 |
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1
Features
2nd Generation EE PROM-based Complex Programmable Logic Devices
– V
CCIO
of 5.0V or 3.3V with 3.3V Operation being 5V Tolerant
– 32 - 256 Macrocells with Enhanced Features
– Pin-compatible with Industry Standard Devices
– Speeds to 5 ns Maximum Pin-to-pin Delay
– Registered Operation to 250 MHz
Enhanced Macrocells with Logic Doubling
Features
– Bury Either Register or COM while Using the Other for Output
– Dual Independent Feedback Allows Multiple Latch Functions per Macrocell
– 5 Product Terms per Macrocell, expandable to 40 per Macrocell with Cascade
Logic, Plus 15 more with Foldback Logic
– D/T/Latch Configurable Flip-flops plus Transparent Latches
– Global and/or per Macrocell Register Control Signals
– Global and/or per Macrocell Output Enable
– Programmable Output Slew Rate per Macrocell
– Programmable Output Open Collector Option per Macrocell
– Fast Registered Input from Product Term
Enhanced Connectivity
– Single Level Switch Matrix for Maximum Routing Options
– Up to 40 Inputs per Logic Block
Advanced Power Management Features
– ITD (Input Transition Detection) Available Individually on Global Clocks, Inputs and
I/O for μA Level Standby Current for “L” Versions
– Pin-controlled 1 mA Standby Mode
– Reduced-power Option per Macrocell
– Automatic Power Down of Unused Macrocells
– Programmable Pin-keeper Inputs and I/Os
Available in Commercial and Industrial Temperature Ranges
Available in All Popular Packages Including PLCC, PQFP and TQFP
EE PROM Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
JTAG Boundary-scan Testing Port per IEEE 1149.1-1990 and 1149.1a-1993
– Pull-up Option on JTAG Pins TMS and TDI
IEEE 1532 Compatibility for Fast In-System Programmability (ISP) via JTAG
PCI-compliant
Security Fuse Feature
ATF15xxSE
Family
Datasheet
ATF1502SE(L)
ATF1504SE(L)
ATF1508SE(L)
ATF1516SE(L)
Preliminary
Rev. 2401D–PLD–09/02
相關PDF資料 |
PDF描述 |
|---|---|
| ATF1508AS-10QI160 | |
| ATF1508JC68-10 | Flash Complex PLD |
| ATF1508SE(L) | ATF1502/04/08/16SE(L) Preliminary [Updated 9/02. 69 Pages] Second Generation Industry Compatible 5V Logic Doubling CPLDs 32-512 Macrocells. standard & low power w/ISP |
| ATF1508Z | High Performance E2PLD |
| ATF1516AL | High Performance EE-Based CPLD |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ATF1508AS-10QI160 | 功能描述:CPLD - 復雜可編程邏輯器件 ASICS RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1508AS-10QL100 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Highperformance EE PLD |
| ATF1508AS-10QL160 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Highperformance EE PLD |
| ATF1508AS-10QU100 | 功能描述:CPLD - 復雜可編程邏輯器件 128 MC CPLD 10NS IND TEMP GRN RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1508AS-15AC100 | 功能描述:CPLD - 復雜可編程邏輯器件 128 MC CPLD 5V ISP CPLD 100 PIN 15NS RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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