參數(shù)資料
型號: ATA6285N-PNQW
廠商: ATMEL CORP
元件分類: 通信及網(wǎng)絡(luò)
英文描述: SPECIALTY TELECOM CIRCUIT, QCC32
封裝: 5 X 5MM, QFN-32
文件頁數(shù): 9/121頁
文件大?。?/td> 9917K
代理商: ATA6285N-PNQW
106
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
Bit5 - T3CNC: Timer3 input Capture Noise Canceler Bit
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is
activated, the input from the Input Capture pin is filtered. The filter function requires four succes-
sive equal valued samples of the Input Capture pin for changing its output. The Input Capture is
therefore delayed by four counter clock (CL3) cycles when the noise canceler is enabled.
Bits 4..3 - T3CE1..0: Timer3 Capture Edge Select Bits 1 - 0
The T3CE1 and T3CE0 bits select the edge from all input capture signals of theTimer3 as shown
Bits 2 to 0 – T3CS2..0: Timer3 Clock Select Bits 2 to 0
The T3CS2, T3CS1, and T3CS0 bits select the input clock (CL3) of theTimer3, shown in Table
Table 3-43.
Timer3 Capture Edge Select Bit Description
T3CE1
T3CE0
Input Capture Edge of Timer3 Capture Input
0
Disable edge detect
0
1
Rising edge
1
0
Falling edge
1
Both edge
Table 3-44.
Timer3 Input Clock Select Bit Description
T3CS2
T3CS1
T3CS0
Input Clock (CL3) of TCNT3
00
0
CLT
00
1
CLK
I/O
01
0
CLK
T0
01
1
CLK
T1
10
0
CLK
T2
10
1
T2I
11
0
T3I
11
1
SCH
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