參數(shù)資料
型號(hào): AT93C86
英文描述: 1K/2K/2K/4K/16K-Bit Microwire Serial E2PROM
中文描述: 1K/2K/2K/4K/16K-Bit微型導(dǎo)線串行E2PROM
文件頁(yè)數(shù): 1/9頁(yè)
文件大?。?/td> 61K
代理商: AT93C86
1
CAT93C46/56/57/66/86
1K/2K/2K/4K/16K-Bit Microwire Serial E
2
PROM
FEATURES
I
High Speed Operation:
– 93C46/56/57/66: 1MHz
– 93C86: 3MHz
I
Low Power CMOS Technology
I
1.8 to 6.0 Volt Operation
I
Selectable x8 or x16 Memory Organization
I
Self-Timed Write Cycle with Auto-Clear
I
Hardware and Software Write Protection
DESCRIPTION
I
Power-Up Inadvertant Write Protection
I
1,000,000 Program/Erase Cycles
I
100 Year Data Retention
I
Commercial, Industrial and Automotive
Temperature Ranges
I
Sequential Read (except 93C46)
I
Program Enable (PE) Pin (93C86 only)
93C46/56/57/66/86 F02
PIN CONFIGURATION
DIP Package (P)
SOIC Package (J)
CMOS E
2
PROM floating gate technology. The devices
are designed to endure 1,000,000 program/erase cycles
and have a data retention of 100 years. The devices are
available in 8-pin DIP, 8-pin SOIC or 8-pin TSSOP
packages.
The CAT93C46/56/57/66/86 are 1K/2K/2K/4K/16K-bit
Serial E
2
PROM memory devices which are configured
as either registers of 16 bits (ORG pin at V
CC
) or 8 bits
(ORG pin at GND). Each register can be written (or read)
serially by using the DI (or DO) pin. The CAT93C46/56/
57/66/86 are manufactured using Catalyst’s advanced
SOIC Package (S)
93C46/56/57/66/86
F01
PIN FUNCTIONS
Pin Name
Function
CS
Chip Select
SK
Clock Input
DI
Serial Data Input
DO
Serial Data Output
V
CC
+1.8 to 6.0V Power Supply
GND
Ground
ORG
Memory Organization
NC
No Connection
PE*
Program Enable
BLOCK DIAGRAM
Note: When the ORG pin is connected to VCC, the X16 organiza
tion is selected. When it is connected to ground, the X8 pin
is selected. If the ORG pin is left unconnected, then an
internal pullup device will select the X16 organization.
SOIC Package (K)
1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
TSSOP Package (U)
*Only For 93C86
CS
SK
DI
DO
VCC
NC (PE*)
ORG
GND
1
2
3
4
8
7
6
5
CS
SK
DI
DO
VCC
NC (PE*)
ORG
GND
1
2
3
4
8
7
6
5
VCC
CS
SK
ORG
GND
DO
DI
1
2
3
4
8
7
6
5
CS
SK
DI
DO
VCC
NC (PE*)
ORG
GND
1
2
3
4
8
7
6
5
NC (PE*)
8
7
6
5
VCC
NC (PE*)
ORG
GND
DI
DO
CS
SK
1
2
3
4
VCC
ADDRESS
DECODER
MEMORY ARRAY
ORGANIZATION
DATA
REGISTER
MODE DECODE
LOGIC
CLOCK
GENERATOR
OUTPUT
BUFFER
DO
SK
CS
PE*
DI
ORG
GND
Doc. No. 25056-00 2/98 M-1
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