參數(shù)資料
型號(hào): AT91SAM9N12-CU
廠商: Atmel
文件頁(yè)數(shù): 19/27頁(yè)
文件大?。?/td> 0K
描述: IC MCU ARM9 217-LFBGA
標(biāo)準(zhǔn)包裝: 126
系列: SAM9N
核心處理器: ARM9
芯體尺寸: 16/32-位
速度: 400MHz
連通性: EBI/EMI,I²C,MMC,SPI,SSC,UART/USART,USB
外圍設(shè)備: DMA,LCD,POR,PWM,WDT
輸入/輸出數(shù): 105
程序存儲(chǔ)器容量: 128KB(128K x 8)
程序存儲(chǔ)器類型: ROM
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 0.9 V ~ 1.1 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: *
包裝: *
26
11096AS–ATARM–4-Oct-11
SAM9N12
‘I’/’O’
Indicates whether the signal is input or output state.
“PU”/”PD”
Indicates whether Pull-up or Pull-down, or nothing is enabled.
“ST”
Indicates if Schmitt Trigger is enabled.
Note:
Example: The PB18 “Reset State” column shows “PIO, I, PU, ST”. That means the line PIO18 is
configured as an Input with Pull-Up and Schmitt Trigger enabled. PD14 reset state is “PIO, I, PU”.
That means PIO Input with Pull-Up. PD15 reset state is “A20, O, PD” which means output address
line 20 with Pull-Down.
8.4.2
PIO Line Selection
Peripheral A, B or C is selected thanks to the PIO_ABCDSR1 and PIO_ABCDSR2 registers in
the PIO Controller Interface.
8.5
Fuse Box Features
SAM9N12 embeds 320 One Time Programming (OTP) bits. When the OTP bit is set, it is seen
as ‘1’. The user interface allows the user to perform the following operations:
8.5.1
Read
10 registers SR0-SR9 that reflect OTP bit state
MSK field (write-once) allow user to mask registers SR1 to SR9
All OTP bits are read as ‘1’ when VDDFUSE is floating, all security features are set.
8.5.2
Write
Done in one 32-bit DATA register
SEL field to select the 32-bit word 0 to 9
Table 8-2.
PIO Line Selection
Px value in PIO_ABCDSR2
Px value in PIO_ABCDSR1
A, B or C
00
A
01
B
10
C
Table 8-3.
Special OTP Bit Description
Bit Number
Bit Name
Function
0W
OTP bit writing is disabled if set
OTP bits are not accessible in test mode
1B
BMS sampling is disabled if set, system boots systematically out of the
ROM code
2
J
JTAG is disabled if set
3-7
Reserved
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